Pulse generation circuit and semiconductor device

• US 9,478,187 B2
• Filed: 05/18/2015
• Issued: 10/25/2016
• Est. Priority Date: 04/04/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyake, Hiroyuki, Toyotaka, Kouhei
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): SKIBINSKI, THOMAS S
• Application Number:
  US14/714,473
• Publication Number:
  US 20150248869A1
• Time in Patent Office: 526 Days
• Field of Search: 327/291, 327293-297, 327/241, 327/242, 327/427, 327/434, 327/437, 327/408, 327/165, 327/166, 327170-177, 377/64, 377/68, 377/78, 377/79, 377/54, 345/42, 326/46
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0404 Matrix technologies
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H03K 3/356026 with synchronous operation H03K3/356034, H03K3/356052 take precedence

Abstract

Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

Claims

1. A pulse generation circuit comprising:

a first unit circuit comprising a first circuit and a second circuit, and a third circuit, the first to third circuits being connected in cascade; and

a second unit circuit comprising a fourth circuit an input of which is connected to the second circuit and an output of which is connected to M (M is an integer of 2 or more) wirings,

wherein the second circuit comprises a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal,

wherein the second circuit is configured to output a first signal from the first output terminal to the first circuit,

wherein the second circuit is configured to output a second signal from the second output terminal to the third circuit,

wherein the second circuit is configured to output a third signal from the third output terminal to the fourth circuit, and

wherein the second circuit is configured to output a fourth signal from the fourth output terminal to the fourth circuit.

2. The pulse generation circuit according to claim 1,

wherein the second circuit is configured to stop the output of the third signal in accordance with a fifth signal input from the first circuit.

3. The pulse generation circuit according to claim 1,

wherein the second circuit is configured to stop the output of the fourth signal in accordance with a sixth signal input from the third circuit.

4. The pulse generation circuit according to claim 1,

wherein the second circuit is configured to control the output of the fourth signal in accordance with a fifth signal input from the first circuit and a sixth signal input from the third circuit.

5. The pulse generation circuit according to claim 1,

wherein the fourth circuit is configured to input a constant voltage to the M wirings.

6. The pulse generation circuit according to claim 1,

wherein the fourth circuit is configured to generate M pulse signals and output the M pulse signals to the M wirings, respectively, and

wherein the second unit circuit is configured to generate the M pulse signals having pulsed widths corresponding to pulse widths of M control signals.

7. A semiconductor device comprising:

2kMN pixel circuits (k, M, and N are each an integer of 2 or more) which are arranged in an dummy circuit array of 2kM rows and N columns;

N source lines to which the pixel circuits in the same columns are connected and to each of which a source signal is input;

a first gate driver and a second gate driver which each generate a gate signal for selecting the pixel circuit to which the source signal is input; and

2kM gate lines to which the pixel circuits in the same rows are connected and to each of which the gate signal is input,

wherein the first gate driver and the second gate driver each comprise the pulse generation circuit according to claim 1.

8. A pulse generation circuit comprising:

a first unit circuit comprising a first circuit, a second circuit, a third circuit, and a dummy circuit, the first to third circuits and the dummy circuit being connected in cascade; and

a second unit circuit comprising a fourth circuit an input of which is connected to the second circuit and an output of which is connected to M (M is an integer of 2 or more) wirings,

wherein the second circuit comprises a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal,

wherein the second circuit is configured to output a first signal from the first output terminal to the first circuit,

wherein the second circuit is configured to output a second signal from the second output terminal to the third circuit,

wherein the second circuit is configured to output a third signal from the third output terminal to the fourth circuit,

wherein the second circuit is configured to output a fourth signal from the fourth output terminal to the fourth circuit, and

wherein the third circuit is configured to output a fifth signal to the dummy circuit and to receive a sixth signal from the dummy circuit.

9. The pulse generation circuit according to claim 8,

wherein the second circuit is configured to stop the output of the third signal in accordance with a seventh signal input from the first circuit.

10. The pulse generation circuit according to claim 8,

wherein the second circuit is configured to stop the output of the fourth signal in accordance with a eighth signal input from the third circuit.

11. The pulse generation circuit according to claim 8,

wherein the second circuit is configured to control the output of the fourth signal in accordance with a seventh signal input from the first circuit and a eighth signal input from the third circuit.

12. The pulse generation circuit according to claim 8,

wherein the fourth circuit is configured to input a constant voltage to the M wirings.

13. The pulse generation circuit according to claim 8,

wherein the fourth circuit is configured to generate M pulse signals and output the M pulse signals to the M wirings, respectively, and

wherein the second unit circuit is configured to generate the M pulse signals having pulsed widths corresponding to pulse widths of M control signals.

14. A semiconductor device comprising:

2kMN pixel circuits (k, M, and N are each an integer of 2 or more) which are arranged in an array of 2kM rows and N columns;

N source lines to which the pixel circuits in the same columns are connected and to each of which a source signal is input;

a first gate driver and a second gate driver which each generate a gate signal for selecting the pixel circuit to which the source signal is input; and

2kM gate lines to which the pixel circuits in the same rows are connected and to each of which the gate signal is input,

wherein the first gate driver and the second gate driver each comprise the pulse generation circuit according to claim 8.