Methods and apparatus for multiple memory maps and multiple page caches in tiered memory

• US 9,478,274 B1
• Filed: 06/25/2014
• Issued: 10/25/2016
• Est. Priority Date: 05/28/2014
• Status: Active Grant

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Michaud, Adrian, Clark, Roy E., Taylor, Kenneth J.
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): WONG, NANCI N
• Application Number:
  US14/314,366
• Time in Patent Office: 853 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 16/00 Information retrieval; Database structures therefor; File system structures therefor
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/653 Page colouring
• CPC Class Codes: G06F 2212/657 : Virtual address space management
• CPC Class Codes: G06F 2212/7201 : Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 : Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/067 : Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/40607 : Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Methods and apparatus for computer systems having first and second memory tier having regions, physical memory having page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier, and virtual memory having mmaps of ones of the regions in the first memory tier and ones of the regions in the second memory tier, wherein the mmaps are associated with multiple ones of the pages caches.

Claims

1. A method, comprising:

for an application host with one or more DRAM storage devices and one or more storage class memory (SCM) storage devices configured to communicate with one or more storage arrays via network;

wherein the one or more storage array comprises at least one SCM storage device,

creating a virtual memory address space including dynamically allocated memory, memory mapped files, and disk backed memory, wherein the virtual memory address space is backed by the one or more DRAM and SCM physical storage devices;

allocating a plurality of user regions in a block device of the one or more SCM storage devices or the storage array, wherein the plurality of user regions is defined in metadata comprising one or more of user region name, location, size, and/or state information;

accessing a first memory tier constructed by memory mapping a first number of user regions into the virtual address space; and

accessing a second memory tier constructed by memory mapping a second number of user regions into the virtual address space,

wherein page caches are mapped to the first number of user regions and the second number of user regions, wherein at least one of the page caches is shared with multiple ones of the user regions in the first memory tier and the user regions in the second memory tier; and

wherein each memory mapped user region in the tiered memory is fronted by a DRAM page cache to which an application issues loads and stores, and data are moved between the tiered memory and DRAM page caches on an on-demand page basis.

2. The method according to claim 1, wherein the page caches are dynamically configurable in size.

3. The method according to claim 1, wherein pages of the page caches are moved earlier in an LRU list when the pages are colored with an important color.

4. The method according to claim 1, wherein the page caches are sized and managed independently of each other.

5. The method according to claim 1, wherein the page caches are associated with different levels of service.

6. The method according to claim 1, wherein the memory maps are created by multiple processes.

7. A computer system, comprising:

an application host, with one or more DRAM storage devices and one or more storage class memory (SCM) storage devices, is configured to communicate with one or more storage arrays via network;

wherein the one or more storage array comprises at least one SCM storage device;

a virtual memory address space including dynamically allocated memory, memory mapped files, and disk backed memory, wherein the virtual memory address space is backed by the one or more DRAM and SCM physical storage devices;

a plurality of user regions allocated in a block device of the one or more SCM storage devices or the storage array, wherein the plurality of user regions is defined in metadata comprising one or more of user region name, location, size, and/or state information;

a first memory tier is constructed by memory mapping a first number of user regions into the virtual address space; and

a second memory tier is constructed by memory mapping of a second number of user regions into the virtual address space;

wherein page caches are mapped to the first number of user regions and the second number of user regions and at least one of the page caches is shared with multiple ones of the user regions in the first memory tier and the user regions in the second memory tier; and

wherein each memory mapped user region in the tiered memory is fronted by a DRAM page cache to which an application issues loads and stores, and data are moved between the tiered memory and DRAM page caches on an on-demand page basis.

8. The system according to claim 7, wherein the page caches are dynamically configurable in size.

9. The system according to claim 7, wherein each memory tier has own DRAM page caches and the page caches are arranged in groups.

10. The system according to claim 7, wherein a color setting of a page of the page cache indicates the page is hot.

11. The system according to claim 7, wherein pages of the page caches are moved earlier in an LRU list when the pages are colored with an important color.

12. The system according to claim 7, wherein the page caches are sized and managed independently of each other.

13. The system according to claim 7, wherein the page caches are associated with different levels of service.

14. The system according to claim 7, wherein the memory maps are created by multiple processes.

15. An article, comprising:

a non-transitory computer readable medium having stored instructions that enable a machine to;

for a system having an application host with one or more DRAM storage devices and one or more storage class memory (SCM) storage devices configured to communicate with one or more storage arrays via network;

wherein the one or more storage array comprises at least one SCM storage device,

create a virtual memory address space including dynamically allocated memory, memory mapped files, and disk backed memory, wherein the virtual memory address space is backed by the one or more DRAM and SCM physical storage devices;

allocate a plurality of user regions in a block device of the one or more SCM storage devices or the storage array, wherein the plurality of user regions is defined in metadata comprising one or more of user region name, location, size, and/or state information;

access a first memory tier constructed by memory mapping a first number of user regions into the virtual address space; and

access a second memory tier constructed by memory mapping a second number of user regions allocated into the virtual address space,

wherein page caches are mapped to the first number of user regions and the second number of user regions and at least one of the page caches is shared with multiple ones of the user regions in the first memory tier and the user regions in the second memory tier; and

wherein each memory mapped user region in the tiered memory is fronted by a DRAM page cache to which an application issues loads and stores, and data are moved between the tiered memory and DRAM page caches on an on-demand page basis.

16. The article according to claim 15, wherein the page caches are dynamically configurable in size.

17. The article according to claim 15, wherein pages of the page caches are moved earlier in an LRU list when the pages are colored with an important color.

18. The article according to claim 15, wherein the page caches are sized and managed independently of each other.

19. The article according to claim 15, wherein the page caches are associated with different levels of service.

20. The article according to claim 15, wherein the memory maps are created by multiple processes.