Programmed data verification for a semiconductor memory device

• US 9,478,280 B2
• Filed: 06/18/2015
• Issued: 10/25/2016
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dae-Yeal, Yu, Jae-Duk, Kang, Dong-Ku
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US14/742,726
• Publication Number:
  US 20160019975A1
• Time in Patent Office: 495 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data. A control logic unit includes a verification operation controller configured to selectively perform, based on a result of comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.

Claims

1. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells configured to store program data;

a sensor configured to generate sensing data by sensing the program data from the memory cell array;

a condition determination unit configured to compare the program data and the sensing data and generate a result of the comparison; and

a control logic unit configured to selectively perform a first verification operation when the comparison result has a first value and a second verification operation when the comparison result has a second value that is different from the first value, wherein;

the first verification operation boosts a verification voltage applied to the memory cell array, during a predetermined period, from a first voltage to a second voltage, which differs from the first voltage, and

the second verification operation boosts the verification voltage applied to the memory cell array, during the predetermined period, from the second voltage to a third voltage, which differs from each of the first and second voltages.

2. The semiconductor memory device of claim 1, wherein program data stored in one memory cell of the plurality of memory cells is at least 2 bits.

3. The semiconductor memory device of claim 1, wherein the program data is programmed to the plurality of memory cells using an incremental step pulse programming (ISPP) process.

4. The semiconductor memory device of claim 1, wherein the second voltage is higher than the first voltage.

5. The semiconductor memory device of claim 1, wherein the condition determination unit comprises:

a verification unit configured to perform the comparison of the program data and the sensing data; and

an identification code generator configured to generate an identification code based on the result of the comparison and transmit the identification code to the control logic unit.

6. The semiconductor memory device of claim 5, wherein a number of bits of the identification code is set based on a number of types of program states stored in each of the plurality of memory cells.

7. The semiconductor memory device of claim 1, wherein:

the control logic unit is configured to generate a control signal for setting a magnitude of the second voltage based on the comparison result; and

the semiconductor device further comprises a voltage generator configured to set the second voltage to the magnitude indicated by the control signal and boost the verification voltage from the second voltage to the third voltage, during the predetermined period, and apply the verification voltage to a word line connected to each of the plurality of memory cells.

8. The semiconductor memory device of claim 7, wherein the voltage generator comprises:

a program voltage generator configured to generate a program voltage when a programming operation is performed and apply the program voltage by controlling a first switch; and

a verification voltage generator configured to generate the verification voltage when a verification operation is performed and apply the verification voltage to the word line by controlling a second switch.

9. The semiconductor memory device of claim 8, wherein the control logic unit is configured to apply the verification voltage to the word line by turning off the first switch and turning on the second switch when a voltage of the word line is reduced to the second voltage from the program voltage.

10. The semiconductor memory device of claim 8, wherein the control logic unit comprises:

a timing controller configured to control on and off timings of the first and second switches; and

an initial voltage controller configured to control a setting operation of an initial voltage of the verification voltage generator.

11. The semiconductor memory device of claim 10, wherein:

when the program voltage generator generates and applies the program voltage to each of the plurality of memory cells, the timing controller turns off the first switch when the program voltage is converted to the first voltage;

the verification voltage generator is configured to turn on the second switch when the first switch is off; and

the initial voltage controller is configured to set the initial voltage to the first voltage.

12. The semiconductor memory device of claim 10, wherein:

when the program voltage generator generates and applies the program voltage to each of the plurality of memory cells, the timing controller turns off the first switch when the program voltage is converted to the second voltage;

the verification voltage generator is configured to turn on the second switch when the first switch is off; and

the initial voltage controller is configured to set the initial voltage to the second voltage.

13. The semiconductor memory device of claim 1, wherein the semiconductor memory device is a flash memory device.

14. The semiconductor device of claim 1, wherein each of the first and second verification operations comprises sensing, with the sensor during the predetermined period, data programmed to the memory cell array using the verification voltage applied to the memory cell array.

15. A semiconductor memory device comprising:

a control logic unit configured to selectively perform a first verification operation when a comparison result between program data and sensing data has a first value and a second verification operation when the comparison result has a second value that is different from the first value, wherein;

the first verification operation boosts a verification voltage applied to a memory cell array, during a predetermined period, from a first voltage to a second voltage, which differs from the first voltage, and

the second verification operation boosts the verification voltage applied to the memory cell array, during the predetermined period, from the second voltage to a third voltage, which differs from each of the first and second voltages.

16. A method executed by a semiconductor memory device, the method comprising:

storing program data in a plurality of memory cells of a memory cell array;

sensing the program data from the memory cell array to generate sensing data;

comparing the program data and the sensing data and generating a result of the comparison; and

selectively performing a first verification operation when the comparison result has a first value and a second verification operation when the comparison result has a second value that is different from the first value, wherein;

the first verification operation boosts a verification voltage applied to the memory cell array, during a predetermined period, from a first voltage to a second voltage, which differs from the first voltage, and

the second verification operation boosts the verification voltage applied to the memory cell array, during the predetermined period, from the second voltage to a third voltage, which differs from each of the first and second voltages.

17. The method of claim 16, wherein storing the program data comprises programming the plurality of memory cells using an incremental step pulse programming (ISPP) process.

18. The method of claim 16, wherein comparing comprises:

performing the comparison of the program data and the sensing data; and

generating an identification code based on the result of the comparison.

19. The method of claim 18, wherein a number of bits of the identification code is set based on a number of types of program states stored in each of the plurality of memory cells.

20. The method of claim 16, wherein each of the first and second verification operations comprises sensing, during the predetermined period, data programmed to the memory cell array using the verification voltage applied to the memory cell array.