Non-volatile memory device having vertical structure and method of operating the same

• US 9,478,291 B2
• Filed: 06/08/2016
• Issued: 10/25/2016
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Jae-hun, Kim, Han-soo, Cho, Won-seok, Jang, Jae-hoon, Shim, Sun-il
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/176,917
• Publication Number:
  US 20160284729A1
• Time in Patent Office: 139 Days
• Field of Search: 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Claims

1. A semiconductor device comprising:

a substrate;

a first ground select electrode on the substrate;

a second ground select electrode on the first ground select electrode;

a plurality of cell electrodes on the second ground select electrode;

a first string select electrode on the plurality of cell electrodes;

a second string select electrode on the first string select electrode;

a string selection line connected to the first string select electrode with a first string select contact plug and connected to the second string select electrode with a second string select contact plug; and

a ground selection line connected to the first ground select electrode with a first ground select contact plug and connected to the second ground select electrode with a second ground select contact plug,

wherein a vertical length of the first string select contact plug is different from a vertical length of the second string select contact plug, and a vertical length of the first ground select contact plug is different from a vertical length of the second ground select contact plug.

2. The semiconductor device of claim 1, wherein the vertical length of the first string select contact plug is greater than the vertical length of the second string select contact plug.

3. The semiconductor device of claim 1, wherein the vertical length of the first ground select contact plug is greater than the vertical length of the second ground select contact plug.

4. The semiconductor device of claim 1, wherein an end of the first ground select electrode comprises an extended portion that extends beyond an end of the second ground select electrode such that the first ground select contact plug is on the extended portion of the first ground select electrode.

5. The semiconductor device of claim 1, wherein an end of the first string select electrode comprises an extended portion that extends beyond an end of the second string select electrode such that the first string select contact plug is on the extended portion of the first string select electrode.

6. The semiconductor device of claim 1, wherein the string selection line and the ground selection line are above a top surface of the second string select electrode.

7. The semiconductor device of claim 6, wherein the plurality of cell electrodes are stacked in a first direction, and the string selection line and the ground selection line are substantially coplanar in a second direction that is substantially perpendicular with respect to the first direction.

8. The semiconductor device of claim 1, wherein the semiconductor device comprises a vertical NAND flash memory.