Phase locked loop including a varainductor
First Claim
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1. A phase locked loop (PLL) comprising:
- a phase frequency detector (PFD) configured to receive a reference frequency and a feedback frequency, the PFD configured to generate a first control signal;
a charge pump (CP) configured to receive the first control signal and generate an analog voltage signal;
a low pass filter (LPF) configured to receive the analog voltage signal and generate a second control signal;
an oscillator circuit configured to receive the second control signal and generate an output signal, the oscillator circuit comprising;
a first varainductor configured to receive an operating voltage;
a second varainductor configured to receive the operating voltage, wherein the second varainductor is electrically connected in parallel with the first varainductor;
a first transistor electrically connected to the first varainductor; and
a second transistor electrically connected to the second varainductor,wherein the first varainductor comprises;
a spiral inductor having a spiral inductor first terminal and a spiral inductor second terminal, wherein the spiral inductor first terminal is an input terminal of the first varainductor, and the spiral inductor second terminal is an output terminal of the first varainductor,a ground ring surrounding at least a ring portion of the spiral inductor, anda floating ring disposed between the ground ring and the spiral inductor,wherein an inductance level of the first varainductor is based on a mutual capacitance between the spiral inductor and the floating ring and a mutual capacitance between the floating ring and the ground ring; and
a frequency divider (FD) configured to receive the output signal and generate the feedback frequency.
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Abstract
A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.
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Citations
19 Claims
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1. A phase locked loop (PLL) comprising:
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a phase frequency detector (PFD) configured to receive a reference frequency and a feedback frequency, the PFD configured to generate a first control signal; a charge pump (CP) configured to receive the first control signal and generate an analog voltage signal; a low pass filter (LPF) configured to receive the analog voltage signal and generate a second control signal; an oscillator circuit configured to receive the second control signal and generate an output signal, the oscillator circuit comprising; a first varainductor configured to receive an operating voltage; a second varainductor configured to receive the operating voltage, wherein the second varainductor is electrically connected in parallel with the first varainductor; a first transistor electrically connected to the first varainductor; and a second transistor electrically connected to the second varainductor, wherein the first varainductor comprises; a spiral inductor having a spiral inductor first terminal and a spiral inductor second terminal, wherein the spiral inductor first terminal is an input terminal of the first varainductor, and the spiral inductor second terminal is an output terminal of the first varainductor, a ground ring surrounding at least a ring portion of the spiral inductor, and a floating ring disposed between the ground ring and the spiral inductor, wherein an inductance level of the first varainductor is based on a mutual capacitance between the spiral inductor and the floating ring and a mutual capacitance between the floating ring and the ground ring; and a frequency divider (FD) configured to receive the output signal and generate the feedback frequency. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A phase locked loop (PLL) comprising:
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a phase frequency detector (PFD); a charge pump (CP) electrically connected to the PFD; a low pass filter (LPF) electrically connected to the CP and configured to generate a control signal; and an oscillator circuit electrically connected to the LPF and configured to receive the control signal and generate an output signal, the oscillator circuit comprising; a first varainductor, a second varainductor electrically connected in parallel with the first varainductor, wherein the first varainductor comprises; a spiral inductor having a spiral inductor first terminal and a spiral inductor second terminal, wherein the spiral inductor first terminal is an input terminal of the first varainductor, and the spiral inductor second terminal is an output terminal of the first varainductor, and wherein the output terminal of the first varainductor is an input terminal of the oscillator circuit, and a floating ring surrounding at least a ring portion of the spiral inductor, and a monolithic three-dimensional integrated circuit (3DIC) comprising; a ground ring disposed in a first tier, and a second tier, wherein the spiral inductor first terminal and the spiral inductor second terminal are disposed in the second tier, the floating ring is disposed in the second tier and is configured to be selectively electrically connected to the ground ring through at least one inter-tier via, wherein an inductance level of the first varainductor is based on a mutual capacitance between the spiral inductor and the floating ring and a mutual capacitance between the floating ring and the ground ring. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A phase locked loop (PLL) comprising:
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a frequency divider configured to receive a PLL output signal and generate a feedback frequency; a phase frequency detector configured to receive the feedback frequency; and an oscillator circuit comprising a varainductor, the oscillator circuit electrically connected to the phase frequency detector and configured to generate the PLL output signal, wherein the varainductor comprises; a spiral inductor over a substrate, the spiral inductor comprising a ring portion, and wherein an output terminal of the varainductor is an output terminal of the spiral inductor, and wherein the output terminal of the varainductor is electrically connected to an input terminal of the oscillator circuit, a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor, a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor, and an array of switches, the array of switches configured to selectively electrically connect the ground ring to the floating ring, wherein an inductance level of the varainductor is based on a mutual capacitance between the spiral inductor and the floating ring and a mutual capacitance between the floating ring and the ground ring. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification