Vertical spiral inductor

• US 9,478,348 B2
• Filed: 06/24/2014
• Issued: 10/25/2016
• Est. Priority Date: 06/24/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Daeik Daniel, Yun, Changhan Hobie, Velez, Mario Francisco, Zuo, Chengjie, Berdy, David Francis, Kim, Jonghae
• Primary Examiner(s): Lian, Mangtin
• Application Number:
  US14/313,241
• Publication Number:
  US 20150371751A1
• Time in Patent Office: 854 Days
• Field of Search: 336/200, 336/223, 336/192, 296/06
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 41/04 for manufacturing coils coils for transformer or inductances H01F27/28
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49075 including permanent magnet or core

Abstract

Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Claims

1. An inductor, comprising:

a first plurality of vias through a substrate, wherein the first plurality of vias are substantially the same height; and

a plurality of conductive traces external to the substrate interconnecting the first plurality of vias,

wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns,

wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane,

wherein the inductor further comprises a plurality of lead out patterns in a second plane perpendicular to the first plane, the plurality of lead out patterns comprising a first lead out and a second lead out,

wherein the first lead out is coupled to a first via of the first plurality of vias, the first via adjacent to at least two other vias of the first plurality of vias, and

wherein the second lead out is coupled to a second via of the first plurality of vias, the second via adjacent to one other via of the first plurality of vias.

2. The inductor of claim 1, further comprising a second plurality of vias external to the substrate, wherein the plurality of conductive traces are coupled to the first plurality of vias by the second plurality of vias.

3. The inductor of claim 1, wherein the inductor is within a ball array.

4. The inductor of claim 3, wherein the inductor is positioned between at least two rows of the ball array.

5. The inductor of claim 1, wherein the substrate is comprised of at least one of glass or silicon.

6. The inductor of claim 1, wherein at least one conductive trace of the plurality of conductive traces is substantially in one dimension.

7. The inductor of claim 1, wherein the at least one conductive trace of the plurality of conductive traces is routed around at least one via in the first plane.

8. The inductor of claim 7, wherein at least one conductive trace of the plurality of conductive traces is routed around at least two vias in the first plane.

9. The inductor of claim 1, further comprising a printed circuit board.

10. A method comprising:

forming a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height; and

forming a plurality of conductive traces external to the substrate, and coupling the plurality of conductive traces to the first plurality of vias,

wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns,

wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane, and

wherein the method further comprises;

forming a plurality of lead out patterns in a second plane perpendicular to the first plane, the plurality of lead out patterns comprising a first lead out and a second lead out;

coupling the first lead out to a first via of the first plurality of vias, the first via adjacent to at least two other vias of the first plurality of vias; and

coupling the second lead out to a second via of the first plurality of vias, the second via adjacent to one other via of the first plurality of vias.

11. The method of claim 10, further comprising forming a second plurality of vias external to the substrate, wherein coupling the plurality of conductive traces to the first plurality of vias is through the second plurality of vias.

12. The method of claim 10, further comprising forming the first plurality of vias within a ball array.

13. The method of claim 12, further comprising positioning the first plurality of vias between at least two rows of the ball array.

14. The method of claim 10, wherein the substrate is comprised of at least one of glass or silicon.

15. The method of claim 10, further comprising forming at least one conductive trace of the plurality of conductive traces in substantially one dimension.

16. The method of claim 10, further comprising routing the at least one conductive trace of the plurality of conductive traces around at least one via in the first plane.

17. The method of claim 16, further comprising routing at least one conductive trace of the plurality of conductive traces around at least two vias in the first plane.

18. An inductor, comprising:

a first plurality of vias through a substrate, wherein the first plurality of vias are substantially the same height;

a second plurality of vias coupled to the first plurality of vias, wherein the second plurality of vias are external to the substrate; and

a plurality of conductive traces interconnecting the second plurality of vias,

wherein the plurality of conductive traces, the first plurality of vias, and the second plurality of vias comprise a plurality of conductive turns,

wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane,

wherein the inductor further comprises a plurality of lead out patterns in a second plane perpendicular to the first plane, the plurality of lead out patterns comprising a first lead out and a second lead out,

wherein the first lead out is coupled to a first via of the first plurality of vias, the first via adjacent to at least two other vias of the first plurality of vias, and

wherein the second lead out is coupled to a second via of the first plurality of vias, the second via adjacent to one other via of the first plurality of vias.