Method for forming a superjunction device with improved ruggedness

• US 9,478,441 B1
• Filed: 08/03/2010
• Issued: 10/25/2016
• Est. Priority Date: 10/21/2003
• Status: Active Grant

• Current Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Inventors: Sridevan, Srikant
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US12/849,782
• Time in Patent Office: 2,275 Days
• Field of Search: 438/132, 438/439, 257/339, 257/E29.06
• US Class Current: 1/1
• CPC Class Codes: H01L 21/38 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.

Claims

1. A method for forming a superjunction device on a substrate having a first conductivity type, the method comprising:

forming a plurality of horizontal first layers of semiconductor material over the substrate, the first layers of semiconductor material being of the first conductivity type, wherein a first layer of said plurality of horizontal first layers is below a second layer of said plurality of horizontal first layers; and

diffusing semiconductor material of a second conductivity type in a plurality of vertically aligned regions on each of the first and second layers, the plurality of vertically aligned regions forming spaced pylons whose widths are narrower than a distance between two adjacent pylons, wherein the vertically aligned regions of the second layer are laterally wider than the vertically aligned regions of the first layer, and wherein a plurality of respective top surfaces of the vertically aligned regions of the second layer are below active regions of the superjunction device.

2. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

3. The method of claim 1, wherein the dimensions of the vertically aligned regions of the second layer are approximately 2% greater than dimensions of the vertically aligned regions of the first layers.

4. The method of claim 3, wherein the vertically aligned regions of the second layer are out of charge balance with a region surrounding the pylon.

5. The method of claim 3, wherein the vertically aligned regions of the first layer are in charge balance with the region surrounding the pylon.

6. The method of claim 1, wherein the pylon has a substantially cylindrical shape.

7. The method of claim 1, wherein the superjunction device has improved avalanche capability.

8. The method according to claim 1, further comprising forming a MOSgated structure atop the second layer, the MOSgated structure having a source contact in a source region, a gate electrode in a channel region positioned above and in contact with a pylon, and a major electrode on a bottom of the substrate.

9. A method for forming a superjunction device having improved avalanche capability, the method comprising:

forming a layer of semiconductor material on a substrate, the substrate and the layer being of N-type conductivity and comprises a plurality of horizontal portions, wherein a first portion of said plurality of horizontal portions is below a second portion of said plurality of horizontal portions;

diffusing semiconductor material of P-type conductivity in a plurality of vertically aligned regions in the layer, the plurality of vertically aligned regions forming spaced pylons whose widths are narrower than a distance between two adjacent pylons and length equals that of the width of the layer,

wherein an area of each pylon farthest from the substrate and constituting a portion of the total area of the pylon, are laterally wide than the rest of the pylon, wherein a top surface of the area of each pylon farthest from the substrate is below an associated active region of the superjunction device.

10. The method of claim 9, wherein the area of each pylon farthest from the substrate and constituting the portion of the total area of the pylon is out of charge balance with a region surrounding the pylon while the rest of the pylon is in charge balance with the region surrounding the pylon.

11. The method of claim 9, wherein the portion is about 10% to 20%.

12. The method of claim 9, wherein the pylon has a substantially cylindrical shape.

13. A method for forming a superjunction device, comprising:

providing a substrate having one conductivity type;

overlaying the substrate with a semiconductor material having the same conductivity type to form a first layer comprising a plurality of horizontal portions, wherein a first portion of said plurality of horizontal portions is below a second portion of said plurality of horizontal portions;

diffusing a semiconductor material of the other conductivity type into the first layer to form a first implant;

forming a second layer over the first layer having the one conductivity type;

diffusing a semiconductor material of the other conductivity type into the second layer to form a second implant laterally wider than that of the first implant, wherein a first portion of the semiconductor material of the other conductivity type forms a first pylon whose width is narrower than a distance between the first pylon and a second portion of the semiconductor material of the other conductivity type forming a second pylon, wherein a top surface of the semiconductor material of the other conductivity type diffused into the second layer is below an active region of the superjunction device.

14. The method of claim 13, further comprising:

forming a MOSgated structure atop the topmost diffusion and having a source and channel region; and

forming a source contact over the source region;

forming a gate electrode over the channel region.

15. The method of claim 13, wherein the one conductivity type is N-type and the other conductivity type is P-type.

16. The method of claim 13, wherein dimensions of the second implant second layer are approximately 2% greater than dimensions of the first implant of the first layer.

17. The method of claim 16, wherein the second implant of the second layer are out of charge balance with a region surrounding the pylon.

18. The method of claim 16, wherein the first implant of the first layer is in charge balance with the region surrounding the first pylon.

19. The method of claim 13, wherein the first pylon has a substantially cylindrical shape.

20. The method of claim 13, wherein the superjunction device has improved avalanche capability.