Methods and apparatus for forming package-on-packages

• US 9,478,474 B2
• Filed: 12/28/2012
• Issued: 10/25/2016
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsu-Hsien, Chen, Chih-Hua, Yeh, En-Hsiang, Liu, Monsen, Chen, Chen-Shien
• Primary Examiner(s): Wagner, Jenny L
• Assistant Examiner(s): McFadden, Michael P
• Application Number:
  US13/729,902
• Publication Number:
  US 20140185264A1
• Time in Patent Office: 1,397 Days
• Field of Search: 361/760
• US Class Current: 1/1
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/18161 of a flip chip
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate

Abstract

Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors.

Claims

1. A package device, comprising:

a first package comprising a first substrate, a first die above the first substrate, a first decoupling capacitor and a second decoupling capacitor above the first substrate, a first molding compound encapsulating the first die, first decoupling capacitor and the second decoupling capacitor, and a first electrical path connecting the first die and the first decoupling capacitor, wherein the first electrical path has a first width in a range from about 8 μ

m to about 44 μ

m, and wherein the first electrical path comprises a first length measured from the first die to the first decoupling capacitor in a range from about 10 μ

m to about 650 μ

m;

a second package comprising a second substrate, a second die above the second substrate, and a second molding compound encapsulating the second die, wherein the second package is a bottom package of a first package-on-package (PoP) device and the first package is a top package of the first PoP device; and

a second electrical path connecting the second die and the second decoupling capacitor, wherein the second electrical path has a second width in a range from about 8 μ

m to about 44 μ

m and a second length in a range from about 10 μ

m to about 650 μ

m, wherein the second electrical path comprises a first redistribution layer (RDL) on the second substrate and does not extend through any dies.

2. The package device of claim 1, wherein the first decoupling capacitor is an aluminum electrolytic capacitor, a solid tantalum capacitor, an aluminum-polymer capacitor, a special polymer capacitor, a poscap capacitor, an os-con capacitor, or a multiple layer ceramic capacitor.

3. The package device of claim 1, wherein the first die comprises a baseband processor, a wireless transceiver, a memory chip, an antenna, or a passive component.

4. The package device of claim 1, wherein the first electrical path comprises a first contact pad of the first die, a second RDL on the first substrate, a first connector connecting the first contact pad and the second RDL, a second contact pad of the first decoupling capacitor, and a second connector connecting the second contact pad and the second RDL.

5. The package device of claim 4, wherein:

the first connector is a mounting stud, a conductive pillar, a solder ball, a micro-bump, or a controlled collapse chip connection (C4) bump; and

the second connector is a mounting stud, a conductive pillar, a solder ball, a micro-bump, or a controlled collapse chip connection (C4) bump.

6. The package device of claim 1, wherein the second electrical path further comprises a third contact pad of the second die, a third connector connecting the third contact pad and the first RDL, a fourth contact pad of the second decoupling capacitor, a third RDL on the first substrate, a fourth connector connecting the fourth contact pad and the third RDL, and a through via connecting the first RDL and the third RDL, wherein the through via extends through the second molding compound.

7. The package device of claim 1, further comprising:

a third die contained within the first package or the second package; and

a third electrical path connecting the third die and the first decoupling capacitor, wherein the third electrical path has a third width in a range from about 8 μ

m to about 44 μ

m and a third length in a range from about 10 μ

m to about 650 μ

m.

15. The package device of claim 1, wherein the first electrical path has a power distribution network (PDN) impedance of less than about 25 ohm when operating at 3 GHz.

16. The package device of claim 1, wherein the second package further comprises a third molding compound, the second substrate being interposed between the second molding compound and the third molding compound.

8. A package-on-package (PoP) device, comprising:

a first package comprising a first substrate, a first redistribution layer (RDL) on the first substrate, a first decoupling capacitor above the first substrate and being connected to the first RDL, and a molding compound encapsulating the first decoupling capacitor;

a second package comprising a second substrate over the first decoupling capacitor, a second RDL on a top surface of the second substrate, a third RDL on a bottom surface of the second substrate, and a first die above the top surface of the second substrate and being connected to the second RDL, wherein a portion of the molding compound is disposed between the first decoupling capacitor and the second substrate;

a first through via (TV) in the molding compound, the first TV connecting the first RDL of the first package and the third RDL of the second package; and

a first electrical path connecting the first die and the first decoupling capacitor, wherein the first electrical path comprises the first TV, wherein the first electrical path has a first width in a range from about 8 μ

m to about 44 μ

m, and wherein the first electrical path has a first length measured from a first contact pad of the first die to a second contact pad of the first decoupling capacitor in a range from about 10 μ

m to about 650 μ

m.

9. The PoP device of claim 8, wherein the first decoupling capacitor is an aluminum electrolytic capacitor, a solid tantalum capacitor, an aluminum-polymer capacitor, a special polymer capacitor, a poscap capacitor, an os-con capacitor, or a multiple layer ceramic capacitor.

10. The PoP device of claim 8 further comprising:

a second TV in the molding compound;

a second die adjacent the first die above the top surface of the second substrate and connected to the second RDL; and

a second electrical path between the second die and the first decoupling capacitor, wherein the second electrical path has a second width in a range from about 8 μ

m to about 44 μ

m and a second length in a range from about 10 μ

m to about 650 μ

m, and wherein the second electrical path comprises the second TV.

11. The PoP device of claim 8, wherein the first electrical path further comprises a first contact pad of the first decoupling capacitor connected to the first RDL by a first connector, and a second contact pad of the first die connected to the second RDL by a second connector.

17. The PoP device of claim 8, wherein the first electrical path has a power distribution network (PDN) impedance of less than about 25 ohm when operating at 3 GHz.

18. The PoP device of claim 8 further comprising a third die in the molding compound, wherein the molding compound is not disposed between the second substrate and the third die.

19. The PoP device of claim 10, wherein the second TV is disposed on an opposing side of the first decoupling capacitor as the first TV.

12. A package device, comprising:

a first substrate;

a first redistribution layer (RDL) on a top surface of the first substrate, a second RDL on a bottom surface of the first substrate, and a through via extending through the first substrate from the top surface to the bottom surface and electrically connecting the first RDL and the second RDL;

a capacitor atop the top surface of the first substrate, the capacitor having a first contact pad and being electrically connected to the first RDL via the first contact pad and a first connector;

a molding compound above the first RDL, the molding compound encapsulating the capacitor;

a first through via (TV) and a second TV extending through the molding compound, the capacitor being interposed between the first TV and the second TV;

a second substrate over the capacitor and the molding compound;

a first integrated circuit (IC) component bonded to a surface of the second substrate opposite the capacitor;

a second IC component adjacent the first IC component and bonded to the surface of the second substrate opposite the capacitor;

a first electrical path electrically connecting the first IC component and the capacitor through the first TV; and

a second electrical path electrically connecting the second IC component and the capacitor through the second TV, wherein the first and the second electrical paths each have a length measured from a respective one of the first and the second IC component to the capacitor of about 10 μ

m to about 650 μ

m and has along the length a narrowest width of from about 8 μ

m to about 44 μ

m.

13. The package device of claim 12, wherein the first electrical path comprises the first contact pad, the first connector, and a portion of the first RDL.

14. The package device of claim 12, wherein the capacitor is a decoupling capacitor.

20. The package device of claim 12 further comprising:

an additional capacitor on an opposing side of the first TV as the capacitor;

a third IC component adjacent the additional capacitor; and

a third electrical path electrically connecting the third IC component and the additional capacitor through the first substrate.