Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP

• US 9,478,485 B2
• Filed: 04/24/2014
• Issued: 10/25/2016
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Bao, XuSheng, Szeto, KwokKeung
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US14/261,252
• Publication Number:
  US 20150001709A1
• Time in Patent Office: 915 Days
• Field of Search: 257/737, 438/109
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 : Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13013 : being rectangular or square
• CPC Class Codes: H01L 2224/13014 : being circular or elliptic
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/14134 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14135 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/24147 : the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/244 : Connecting portions
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/8236 : Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.

Claims

1. A method of making a semiconductor device, comprising:

providing a first semiconductor die including a plurality of contact pads formed over a central region of the first semiconductor die;

forming a first conductive layer over the first semiconductor die and extending from the contact pads to a peripheral region of the first semiconductor die;

forming a plurality of first interconnect structures over the first conductive layer in the peripheral region of the first semiconductor die;

forming a first protective coating over the first semiconductor die and around the first interconnect structures;

removing a portion of the first semiconductor die opposite the first interconnect structures after forming the first protective coating;

removing the first protective coating after removing the portion of the first semiconductor die;

providing a second semiconductor die including a plurality of bumps formed on an active surface of the second semiconductor die;

disposing the first semiconductor die over the second semiconductor die with the bumps oriented away from the first semiconductor die and with the first interconnect structures disposed around the second semiconductor die;

depositing an encapsulant around the first semiconductor die and second semiconductor die; and

forming a second conductive layer contacting the bumps and first interconnect structures.

2. The method of claim 1, further including removing a portion of the second semiconductor die.

3. The method of claim 1, further including:

forming a second protective coating over the second semiconductor die;

removing a portion of the second semiconductor die after forming the second protective coating; and

removing the second protective coating after removing the portion of the second semiconductor die.

4. The method of claim 1, wherein the first protective coating includes a water soluble polymer material.

5. The method of claim 1, wherein the first interconnect structures include a non-fusible portion and a fusible portion.

6. The method of claim 1, further including forming a plurality of second interconnect structures across the central region of the first semiconductor die to divide the central region of the first semiconductor die into first and second regions devoid of the first and second interconnect structures.

7. The method of claim 6, further including:

disposing the second semiconductor die in the first region; and

disposing a third semiconductor die in the second region.

8. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a first conductive layer over the first semiconductor and extending from a central region of the first semiconductor die to a peripheral region of the first semiconductor die;

forming a plurality of first interconnect structures over the first conductive layer in the peripheral region of the first semiconductor die;

providing a second semiconductor die including a plurality of bumps formed over an active surface of the second semiconductor die;

providing a carrier;

disposing the second semiconductor die over the carrier with the bumps oriented toward the carrier;

disposing the first semiconductor die with the first interconnect structures over the second semiconductor die on the carrier, wherein the first interconnect structures are disposed around the second semiconductor die;

depositing an encapsulant over the first semiconductor die, second semiconductor die, and carrier and further around the first interconnect structures;

removing the carrier; and

forming a second interconnect structure over the encapsulant and in contact with the first interconnect structures and bumps after removing the carrier.

9. The method of claim 8, further including removing a portion of the first semiconductor die after forming the first interconnect structures.

10. The method of claim 8, wherein forming the first interconnect structures includes forming a plurality of conductive pillars.

11. The method of claim 8, further including:

forming a protective coating over an active surface of the first semiconductor die;

removing a portion of the first semiconductor die opposite the active surface after forming the protective coating; and

removing the protective coating after removing the portion of the first semiconductor die.

12. The method of claim 8, further including forming a plurality of second interconnect structures across the central region of the first semiconductor die to divide the central region of the first semiconductor die into a first region and a second region devoid of the first and second interconnect structures.

13. The method of claim 12, further including:

disposing the second semiconductor die in the first region; and

disposing a third semiconductor die in the second region.

14. The method of claim 8, further including forming a second conductive layer over the first interconnect structures and active surface of the second semiconductor die after depositing the encapsulant.

15. The method of claim 8, further including:

forming a protective coating over the second semiconductor die;

removing a portion of the second semiconductor die after forming the protective coating; and

removing the protective coating after removing the portion of the second semiconductor die.

16. A semiconductor device, comprising:

a first semiconductor die;

a plurality of first interconnect structures formed over a peripheral region of the first semiconductor die;

a second semiconductor die disposed over the first semiconductor die and between the first interconnect structures with an active surface of the second semiconductor die oriented away from the first semiconductor die and a gap between the first semiconductor die and second semiconductor die;

a plurality of second interconnect structures formed on the active surface of the second semiconductor die opposite the first semiconductor die;

an encapsulant deposited around the first semiconductor die and second semiconductor die and further in the gap over an entirety of a second surface of the second semiconductor die opposite the active surface; and

a first conductive layer formed over and contacting the first interconnect structures and second interconnect structures.

17. The semiconductor device of claim 16, wherein a height of the second semiconductor die is less than a height of the first interconnect structures.

18. The semiconductor device of claim 16, wherein the first interconnect structures include:

a conductive pillar; and

a bump formed over the conductive pillar.

19. The semiconductor device of claim 16, further including a plurality of third interconnect structures formed across a central region of the first semiconductor die and dividing the central region of the first semiconductor die into a first region and second region devoid of the first and third interconnect structures.

20. The semiconductor device of claim 19, wherein the second semiconductor die is disposed in the first region between the first and third interconnect structures.

21. The semiconductor device of claim 20, further including a third semiconductor die disposed in the second region between the first and third interconnect structures.

22. The semiconductor device of claim 16, further including a second conductive layer extending from a contact pad in a central region of the first semiconductor die to the peripheral region of the first semiconductor die.

23. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

forming a plurality of first interconnect structures over the first semiconductor die;

providing a second semiconductor die including a plurality of bumps formed over an active surface of the second semiconductor die;

providing a carrier;

disposing the second semiconductor die over the carrier with the bumps oriented toward the carrier;

disposing the first semiconductor die with the first interconnect structures over the second semiconductor die on the carrier, wherein the second semiconductor die is disposed between the first interconnect structures and the first interconnect structures contact the carrier leaving a gap between the first semiconductor die and second semiconductor die;

depositing an encapsulant over the first semiconductor die, second semiconductor die, and carrier and further around the first interconnect structures and in the gap over an entirety of a second surface of the second semiconductor die opposite the active surface;

removing the carrier; and

forming a second interconnect structure over the encapsulant and in contact with the first interconnect structures and bumps after removing the carrier.

24. The method of claim 23, further including:

forming a protective coating over the first semiconductor die and around the first interconnect structures;

removing a portion of the first semiconductor die after forming the protective coating; and

removing the protective coating after removing the portion of the first semiconductor die.

25. The method of claim 24, wherein the protective coating includes a water soluble polymer material.

26. The method of claim 23, further including:

forming a protective coating over the second semiconductor die;

removing a portion of the second semiconductor die after forming the protective coating;

removing the protective coating after removing the portion of the second semiconductor die.

27. The method of claim 23, wherein forming the first interconnect structures includes forming a plurality of conductive pillars.