Three dimensional memory device containing aluminum source contact via structure and method of making thereof

• US 9,478,495 B1
• Filed: 10/26/2015
• Issued: 10/25/2016
• Est. Priority Date: 10/26/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Xia, Jilin, Pachamuthu, Jayavel, Rabkin, Peter, Petti, Christopher
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US14/922,516
• Time in Patent Office: 365 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53204 Conductive materials
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 : characterised by the boundary region between the core and peripheral circuit regions

Abstract

A low-stress contact via structure for a device employing an alternating stack of insulating layers and electrically conductive layers over a substrate can be formed by forming a trench extending to the substrate through the alternating stack. After formation of an insulating spacer and a diffusion barrier layer, a remaining volume of the trench can be filled with a combination of an aluminum portion and a non-metallic material portion to form a contact via structure. The non-metallic material portion can include a semiconductor material portion or a dielectric material portion, and can prevent reflow of the aluminum portion and generation of a cavity in subsequent thermal processes. If a semiconductor material portion is employed, the aluminum portion and the semiconductor material portion can exchange places during a metal induced crystallization anneal process of the semiconductor material.

Claims

1. A structure comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate; and

a contact via structure extending through the alternating stack;

wherein the contact via structure comprises;

an electrically conductive diffusion barrier layer; and

a combination of an aluminum portion and a non-metallic material portion, wherein the combination of the aluminum portion and the non-metallic material portion is laterally surrounded by the diffusion barrier layer.

2. The structure of claim 1, wherein:

lateral sides of the combination of the aluminum portion and the non-metallic material portion are surrounded by the diffusion barrier layer; and

the diffusion barrier layer comprises a conductive metallic compound of at least one elemental metal and at least one non-metallic element.

3. The structure of claim 1, wherein:

the non-metallic material portion comprises a semiconductor material portion; and

the semiconductor material portion laterally surrounds the aluminum portion.

4. The structure of claim 3, wherein:

the semiconductor material portion comprises an aluminum doped single crystal silicon portion or an aluminum doped polysilicon portion;

an outer sidewall of the semiconductor material portion contacts an inner sidewall of the diffusion barrier layer; and

an inner sidewall of the semiconductor material portion contacts an outer sidewall of the aluminum portion.

5. The structure of claim 3, wherein:

a bottom surface of the aluminum portion contacts a top surface of the horizontal portion of the diffusion barrier layer; and

a bottom surface of the semiconductor material portion is located above, and is vertically spaced from, a top surface of a horizontal portion of the diffusion barrier layer by the aluminum portion.

6. The structure of claim 1, wherein the non-metallic material portion comprises a dielectric material portion.

7. The structure of claim 6, wherein the aluminum portion laterally surrounds the dielectric material portion.

8. The structure of claim 7, wherein:

the dielectric material portion comprises a dielectric material selected from silicon oxide, silicon nitride, and a dielectric metal oxide;

an outer sidewall of the aluminum portion contacts an inner sidewall of the diffusion barrier layer; and

an inner sidewall of the aluminum portion contacts a sidewall of the dielectric material portion.

9. The structure of claim 1, wherein each of the aluminum portion and the non-metallic material portion extends from a first horizontal plane including a top surface of a bottommost layer within the alternating stack to a second horizontal plane including a top surface of the topmost layer within the alternating stack.

10. The structure of claim 1, wherein:

a bottom of the contact via structure contacts a top surface of a doped semiconductor portion;

the electrically conductive layers comprise word lines;

the doped semiconductor portion comprises a source region located in the substrate;

a horizontal portion of the diffusion barrier layer contacts the top surface of the source region and a bottom surface of the aluminum portion; and

the non-metallic portion is vertically spaced from the horizontal portion of the diffusion barrier layer by the aluminum portion.

11. The structure of claim 10, further comprising:

a source line contacting a top surface of the aluminum portion and a top surface of the non-metallic material portion;

an insulating spacer laterally surrounding the contact via structure and electrically isolating the contact via structure from the word lines; and

at least one memory stack structure extending through the alternating stack, wherein each of the at least one memory stack structure comprises, from inside to outside;

a semiconductor channel;

a tunneling dielectric layer laterally surrounding the semiconductor channel; and

charge storage regions laterally surrounding the tunneling dielectric layer.

12. The structure of claim 1, wherein:

the structure comprises a three-dimensional memory device that comprises a vertical NAND device formed in a device region;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

13. A method of manufacturing a structure, comprising:

forming an alternating stack comprising insulating layers and electrically conductive layers over a substrate;

forming a trench extending to the substrate through the alternating stack;

forming an insulating spacer on a sidewall of the trench, wherein a cavity is provided within the insulating spacer;

forming an electrically conductive diffusion barrier layer in the cavity; and

filling a remaining portion of the cavity with a combination of an aluminum portion and a non-metallic material portion, wherein the combination of the aluminum portion and the non-metallic material portion and a portion of the diffusion barrier layer constitute a contact via structure extending through the alternating stack and contacting a top surface of a doped semiconductor portion.

14. The method of claim 13, wherein the combination of the aluminum portion and the non-metallic material portion is formed by:

depositing aluminum on the metallic barrier layer;

depositing a non-metallic material on the deposited aluminum; and

removing portions of the deposited aluminum and deposited non-metallic material from above a horizontal plane located above the alternating stack.

15. The method of claim 14, wherein the non-metallic material comprises a semiconductor material.

16. The method of claim 15, wherein the semiconductor material comprises amorphous silicon or smaller grain size polysilicon.

17. The method of claim 16, further comprising annealing the structure to perform a metal induced crystallization of the amorphous silicon or smaller grain size polysilicon to convert the amorphous silicon or smaller grain size polysilicon to either single crystal silicon or larger grain size polysilicon.

18. The method of claim 17, wherein the aluminum portion and the semiconductor material exchange places during the metal induced crystallization such that a portion of the single crystal silicon or larger grain size polysilicon surrounds a vertically extending portion of aluminum after the step of annealing.

19. The method of claim 18, wherein the single crystal silicon or larger grain size polysilicon comprises aluminum doped single crystal silicon or larger grain size polysilicon.

20. The method of claim 14, wherein the non-metallic material comprises a dielectric material selected from silicon oxide, silicon nitride, and a dielectric metal oxide.

21. The method of claim 13, further comprising forming a salicide portion in the contact via structure.

22. The method of claim 13, further comprising:

forming an in-process alternating stack of the insulating layers and sacrificial material layers;

forming at least one memory stack structure extending through the in-process stack;

removing the sacrificial material layers by introducing into the trench an etchant that etches the sacrificial material layers selective to the insulating layers through the trench; and

forming the electrically conductive layers in recesses formed by removal of the sacrificial material layers, thereby forming the alternating stack of the insulating layers and the electrically conductive layers.

23. The method of claim 22, wherein:

the contact via structure comprises a source contact via structure;

the doped semiconductor portion comprises a source region;

the electrically conductive layers comprise word lines; and

each of the at least one memory stack structure comprises, from inside to outside;

a semiconductor channel;

a tunneling dielectric layer laterally surrounding the semiconductor channel; and

charge storage regions laterally surrounding the tunneling dielectric layer.

24. The method of claim 13, wherein:

the structure comprises a three-dimensional memory device that comprises a vertical NAND device formed in a device region;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

25. A method of manufacturing a structure, comprising:

forming an alternating stack comprising insulating layers and electrically conductive layers over a substrate;

forming an opening extending through the alternating stack;

forming an insulating spacer on a sidewall of the opening, wherein a cavity is provided within the insulating spacer;

forming an electrically conductive diffusion barrier layer in the cavity; and

filling a remaining portion of the cavity with a combination of an aluminum portion and a non-metallic material portion, wherein the combination of the aluminum portion and the non-metallic material portion and a portion of the diffusion barrier layer constitute a contact via structure extending through the alternating stack.

26. The method of claim 25, wherein:

the non-metallic material comprises amorphous silicon or smaller grain size polysilicon; and

the combination of the aluminum portion and the non-metallic material portion is formed by;

depositing aluminum on the metallic barrier layer;

depositing a non-metallic material on the deposited aluminum; and

removing portions of the deposited aluminum and deposited non-metallic material from above a horizontal plane located above the alternating stack.

27. The method of claim 26, further comprising annealing the structure to perform a metal induced crystallization of the amorphous silicon or smaller grain size polysilicon to convert the amorphous silicon or smaller grain size polysilicon to either single crystal silicon or larger grain size polysilicon, wherein the aluminum portion and the semiconductor material exchange places during the metal induced crystallization such that a portion of the single crystal silicon or larger grain size polysilicon surrounds a vertically extending portion of aluminum after the step of annealing.