Microelectronic assemblies with cavities, and methods of fabrication

• US 9,478,504 B1
• Filed: 06/19/2015
• Issued: 10/25/2016
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Shen, Hong, Wang, Liang, Katkar, Rajesh, Woychik, Charles G., Gao, Guilian
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/745,237
• Time in Patent Office: 494 Days
• Field of Search: 438/667
• US Class Current: 1/1
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92225 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/053 : the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/145 : Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/15 : Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/16315 : Shape
• CPC Class Codes: H01L 2924/1632 : Disposition
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/16787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid'"'"'s legs (520) surround the cavity and extend down below the top surface of the interposer'"'"'s substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid'"'"'s legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Claims

1. A fabrication method comprising:

obtaining a first structure comprising one or more cavities;

obtaining a second structure comprising a first microelectronic component and one or more second microelectronic components, wherein;

the first microelectronic component comprises a first substrate, the first microelectronic component comprising first circuitry, wherein the first substrate comprises a first side and one or more first holes in the first side;

each second microelectronic component comprises one or more respective second substrates, each second microelectronic component comprising respective second circuitry, each second microelectronic component being attached to the first side of the first substrate, wherein the second circuitry of at least one second microelectronic component is electrically coupled to the first circuitry;

attaching the first structure to the second structure so that at least one second microelectronic component is located in at least one of the one or more cavities and so that at least a portion of a sidewall of at least one of the one or more cavities is located in a corresponding first hole such that at least a portion of a sidewall of the corresponding first hole extends laterally along a straight line adjacent to at least one second microelectronic component located in said cavity, and such that said at least a portion of a sidewall of at least one of the one or more cavities extends laterally along the portion of the corresponding first hole.

2. The fabrication method of claim 1 wherein during the attaching operation, the one or more first holes do not go through the substrate of the first microelectronic component;

and

the method further comprises, after said attaching, thinning the first substrate to turn the one or more first holes into one or more through-holes in the first substrate.

3. The fabrication method of claim 2 wherein the first circuitry comprises one or more conductive vias at least partially located in the first substrate and electrically coupled to the second circuitry of at least one second microelectronic component;

and

said thinning of the first substrate exposes the one or more conductive vias on a second side of the first substrate, the second side being opposite to the first side of the first substrate.

5. The fabrication method of claim 1 wherein after the attaching operation, at least a portion of a sidewall of at least one cavity does not adhere to the second structure.

6. The fabrication method of claim 1 wherein the attaching operation causes the second structure to adhere to one or more regions inside the one or more cavities but not to any other regions, the one or more regions being at a distal end from the first substrate.

10. The method of claim 1 further comprising, after said attaching, dicing the first and second structures to remove a portion of at least one first hole and to expose a portion of the first structure inside the at least one first hole.

4. A fabrication method comprising:

obtaining a first structure comprising one or more cavities;

obtaining a second structure comprising a first microelectronic component and one or more second microelectronic components, wherein;

the first microelectronic component comprises a first substrate, the first microelectronic component comprising first circuitry, wherein the first substrate comprises a first side and one or more first holes in the first side;

each second microelectronic component comprises one or more respective second substrates, each second microelectronic component comprising respective second circuitry, each second microelectronic component being attached to the first side of the first substrate, wherein the second circuitry of at least one second microelectronic component is electrically coupled to the first circuitry;

attaching the first structure to the second structure so that at least one second microelectronic component is located in at least one of the one or more cavities and so that at least a portion of a sidewall of at least one of the one or more cavities is located in a corresponding first hole;

wherein during the attaching operation, the one or more first holes do not go through the substrate of the first microelectronic component; and

the method further comprises, after said attaching, thinning the first substrate to turn the one or more first holes into one or more through-holes in the first substrate;

wherein the one or more first holes comprise a hole containing at least a portion of a sidewall of at least one of the one or more cavities and completely laterally surrounding at least one second microelectronic component.

7. A fabrication method comprising:

obtaining an assembly comprising;

a first structure comprising one or more cavities;

a second structure attached to the first structure and comprising a first microelectronic component and one or more second microelectronic components, wherein;

the first microelectronic component comprises a first substrate, the first microelectronic component comprising first circuitry; and

each second microelectronic component comprises one or more respective second substrates, each second microelectronic component comprising a respective second circuitry, the one or more second microelectronic components being attached to a first side of the first substrate, wherein the second circuitry of at least one second microelectronic component is electrically coupled to the first circuitry;

wherein at least one second microelectronic component is located in at least one of the cavities;

wherein the method further comprises thinning the assembly, wherein the thinning of the assembly comprises simultaneous thinning of (i) the second structure, and (ii) the first structure at a sidewall of the at least one of the cavities.

8. The method of claim 7 wherein the thinning of the assembly comprises simultaneous thinning of the first substrate and the sidewall of the at least one of the cavities.

9. The method of claim 8 wherein the first circuitry comprises one or more conductive vias at least partially located in the first substrate and electrically coupled to the second circuitry of at least one second microelectronic component;

and

said thinning of the assembly exposes the one or more conductive vias on a second side of the first substrate, the second side being opposite to the first side of the first substrate.