Semiconductor device and manufacturing method of the same

• US 9,478,530 B2
• Filed: 01/20/2016
• Issued: 10/25/2016
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakazawa, Yoshito, Yatsuda, Yuji
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): Singal, Ankush
• Application Number:
  US15/001,767
• Publication Number:
  US 20160148923A1
• Time in Patent Office: 279 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Claims

1. A semiconductor device comprising:

a drain region of a field-effect transistor formed over a semiconductor substrate;

a channel region of the field-effect transistor formed over the drain region;

a source region of the field-effect transistor formed over the channel region;

a trench penetrating the channel region and reaching the drain region;

a first gate insulating film of the field-effect transistor formed in the trench and disposed at a lower part of the trench;

a first gate electrode of the field-effect transistor formed over the first gate insulating film in the trench and disposed at the lower part of the trench;

a second gate insulating film formed in the trench and disposed at a upper part of the trench; and

a second gate electrode of the field-effect transistor formed over the second gate insulating film in the trench and disposed at the upper part of the trench,

wherein the first gate electrode includes a first polysilicon film,

wherein the second gate electrode includes a second polysilicon film,

wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film, and

wherein a thickness of the first gate insulating film is thicker than a thickness of the second gate insulating film.

2. A semiconductor device according to the claim 1,

wherein a conductivity type of the first polysilicon film is n-type, and

wherein a conductivity type of the second polysilicon film is n-type.

3. A semiconductor device according to the claim 2,

wherein a conductivity type of the drain region is n-type,

wherein a conductivity type of the channel region is p-type, and

wherein a conductivity type of the source region is n-type.