Semiconductor memory device and method of fabricating the same

• US 9,478,561 B2
• Filed: 12/07/2015
• Issued: 10/25/2016
• Est. Priority Date: 01/30/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chaeho, Yang, Sangryol, Lee, Woong, Lim, SeungHyun
• Primary Examiner(s): Mondt, Johannes P
• Application Number:
  US14/960,776
• Publication Number:
  US 20160225785A1
• Time in Patent Office: 323 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a stack on the substrate, the stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on the substrate;

a cell channel structure penetrating the stack,

the cell channel structure including a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern,

the first channel pattern contacting the first semiconductor pattern,

the first semiconductor pattern extending to a first height from a surface of the substrate to a top surface of the first semiconductor pattern; and

a first dummy channel structure on the substrate,

the first dummy channel structure being spaced apart from the stack,

the first dummy channel structure including a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern,

the second channel pattern contacting the second semiconductor pattern,

the second semiconductor pattern extending to a second height from the surface of the substrate to a top surface of the second semiconductor pattern, and

the first height being greater than the second height.

2. The device of claim 1, further comprising:

a bit line connected to the cell channel structure.

3. The device of claim 1, wherein

the cell channel structure further includes a first data storing pattern between the stack and the first channel pattern,

the first dummy channel structure further includes a second data storing pattern in contact with a sidewall of the second channel pattern,

a material in the first channel pattern is the same as a material in the second channel pattern, and

a material in the first data storing pattern is the same as a material in the second data storing pattern.

4. The device of claim 1, wherein

the substrate includes a cell region, a peripheral region spaced apart from the cell region, and a boundary region between the cell region and the peripheral region,

the cell region includes a cell array region and a connection region adjacent to the cell array region,

the stack is on the cell region,

the stack extends from the cell array region to the connection region in a first direction, and

an edge part of the stack has a stepwise structure on the connection region.

5. The device of claim 4, further comprising:

a mold insulating layer that covers the edge part of the stack, wherein

the mold insulating layer is on the connection region, the boundary region, and the peripheral region,

the first dummy channel structure penetrates the mold insulating layer, and

the first dummy channel structure contacts the substrate.

6. The device of claim 5, further comprising:

a second dummy channel structure on the connection region, wherein

the second dummy channel structure penetrates the mold insulating layer and the edge part of the stack,

the second dummy channel structure includes a third semiconductor pattern and a third channel pattern,

the third channel pattern is on the third semiconductor pattern, and

the third channel pattern is in contact with the third semiconductor pattern.

7. The device of claim 6, wherein the first dummy channel structure in plan view has one of a circular shape, an oval shape, and a bar shape.

8. The device of claim 4, further comprising:

a peripheral circuit device on the peripheral region,

wherein the peripheral circuit device includes a peripheral gate insulating layer, a peripheral gate electrode, and peripheral source/drain regions.

9. The device of claim 1, further comprising:

a gate dielectric layer contacting a sidewall of the first semiconductor pattern,

wherein the gate dielectric layer is not adjacent to a sidewall of the second semiconductor pattern.

10. A semiconductor memory device, comprising:

a substrate including a cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and a boundary region between the connection region of the cell region and the peripheral region;

stacks on the cell region, the stacks spaced apart from each other in a first direction, each of the stacks including gate electrodes and insulating layers that are alternately and repeatedly stacked on the substrate and having an edge part on the connection region;

cell channel structures penetrating the stacks on the cell array region, each of the cell channel structures including a first semiconductor pattern and a first channel pattern that is on the first semiconductor pattern and in contact with the first semiconductor pattern;

first dummy channel structures penetrating the stacks on the connection region, each of the first dummy channel structures including a second semiconductor pattern and a second channel pattern that is on the second semiconductor pattern and in contact with the second semiconductor pattern; and

a second dummy channel structure on the boundary region, the second dummy channel structure including a third semiconductor pattern and a third channel pattern that is on the third semiconductor pattern and in contact with the third semiconductor pattern.

11. The device of claim 10, wherein

the first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern,

the second semiconductor pattern of at least one of the first dummy channel structures adjacent to the third semiconductor pattern further includes a first sub-semiconductor pattern,

the first sub-semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the first sub-semiconductor pattern,

the third semiconductor pattern extends to a third height from the surface of the substrate to a top surface of the third semiconductor pattern, and

the second and third heights are smaller than the first height.

12. The device of claim 11, wherein

the second semiconductor pattern of at least one of the first dummy channel structures adjacent to the first semiconductor patterns further includes a second sub-semiconductor pattern,

the second sub-semiconductor pattern extends to a fourth height from the surface of the substrate to a top surface of the second sub-semiconductor pattern, and

the fourth height is greater than the second and third heights.

13. The device of claim 12, further comprising:

a peripheral circuit device on the peripheral region; and

peripheral contacts connected to the peripheral circuit device on the peripheral region,

wherein the peripheral circuit device includes a peripheral gate insulating layer, a peripheral gate electrode, and peripheral source/drain regions.

14. The device of claim 12, further comprising:

a mold insulating layer on the peripheral region, the boundary region, and the connection region, wherein

the mold insulating layer covers the edge parts of the stacks, and

the first and second dummy channel structures of the stacks penetrate the mold insulating layer.

15. The device of claim 12, wherein

each of the cell channel structures further includes a first data storing pattern in contact with a sidewall of the first channel pattern,

each of the first dummy channel structures further includes a second data storing pattern in contact with a sidewall of the second channel pattern,

the second dummy channel structure further includes a third data storing pattern in contact with a sidewall of the third channel pattern,

the first, second, and third channel patterns include a same channel material, and

the first, second, and third data storing patterns include a same data storing material.

16. A semiconductor memory device, comprising:

a substrate including a cell region including a cell array region and a connection region, a peripheral region spaced apart from the cell region, and a boundary region between the cell region and the peripheral region;

a stack on the cell region, the stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on each other on the substrate; and

a plurality of channel structures spaced apart from each other on the substrate,

the plurality of channel structures each including a channel pattern on top of a semiconductor pattern,

the plurality of channel structures including cell channel structures on the cell array region,

the cell channel structures extending vertically through the stack,

a bottom of the channel pattern of the cell channel structures being spaced apart from a surface of the substrate by a first height,

the plurality of channel structures including a dummy channel structure on the boundary region, and

a bottom of the channel pattern of the dummy channel structure being spaced apart from the surface of the substrate by a second height that is less than the first height.

17. The device of claim 16, wherein

some of the plurality of channel structures include gate dielectric layers contacting sidewalls of the semiconductor patterns,

some of the gate dielectric layers contact sidewalls of the semiconductor patterns of the cell channel structures, and

none of the gate dielectric layers are adjacent to a sidewall of the semiconductor pattern of the dummy channel structure.

18. The device of claim 16, wherein

the plurality of channel structures include at least one first dummy channel structure on the connection region,

the dummy channel structure on the boundary region is a second dummy channel structure,

the semiconductor patterns of the cell channel structures extend from the surface of the substrate to the first height,

the semiconductor patterns of the second dummy channel structure extend from the surface of the substrate to the second height,

the semiconductor pattern of one first dummy channel structure of the at least one first dummy channel structure extends from the surface of the substrate to a height that is between the first height and the second height.

19. The device of claim 16, further comprising:

a mold insulating layer covering an edge part of the stack and the boundary region, wherein

the dummy channel structure penetrates the mold insulating layer, and

the cell channel structures do not penetrate the mold insulating layer.

20. The device of claim 16, further comprising:

bit lines connected to the cell channel structures, wherein

the plurality of channel structures include data storing patterns surrounding the channel patterns of the plurality of channel structures.