Semiconductor device
First Claim
1. A semiconductor device comprising:
- a transistor comprising;
a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and
a gate electrode over the channel formation region with an insulating film interposed therebetween,wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×
10−
17 A/μ
m when a channel length of the transistor is 3 μ
m, voltage between an source electrode and an drain electrode is 1V and gate voltage is in a range of −
5V to −
20V.
1 Assignment
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Accused Products
Abstract
An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
155 Citations
17 Claims
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1. A semiconductor device comprising:
-
a transistor comprising; a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and a gate electrode over the channel formation region with an insulating film interposed therebetween, wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×
10−
17 A/μ
m when a channel length of the transistor is 3 μ
m, voltage between an source electrode and an drain electrode is 1V and gate voltage is in a range of −
5V to −
20V. - View Dependent Claims (2, 3, 4, 5)
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6. A memory device comprising:
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a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; and a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the fourth wiring, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the fourth wiring, wherein a gate electrode of the third transistor and a gate electrode of the fourth transistor are each electrically connected to the third wiring, wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the first wiring, wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring, wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to the other of the source electrode and the drain electrode of the first transistor, and the other of the source electrode and the drain electrode of the third transistor, and a gate electrode of the sixth transistor, wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the other of the source electrode and the drain electrode of the second transistor, the other of the source electrode and the drain electrode of the fourth transistor, and a gate electrode of the fifth transistor, wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the fifth wiring, and wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the fifth wiring, wherein the fifth transistor comprising, a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and the gate electrode over the channel formation region with an insulating film interposed therebetween, and wherein a value of off-state current through the crystalline oxide semiconductor layer of the fifth transistor is less than or equal to 1×
10−
17 A/μ
m when a channel length of the fifth transistor is 3 μ
m, voltage between the source electrode and the drain electrode is 1V and gate voltage is in a range of −
5V to −
20V. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A memory device comprising:
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a capacitor; a transistor comprising; a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and a gate electrode over the channel formation region with an insulating film interposed therebetween, and a first wiring, a second wiring, and a third wiring, wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×
10−
17 A/μ
m when a channel length of the transistor is 3 μ
m, voltage between a source electrode and a drain electrode is 1V and gate voltage is in a range of −
5V to −
20V, andwherein the first wiring is electrically connected to the gate electrode of the transistor, wherein the second wiring is electrically connected to one of the source electrode and the drain electrode of the transistor, wherein the other of the source electrode and the drain electrode of the transistor is electrically connected to one of a pair of electrodes of the capacitor, and wherein the other of the pair of the electrodes of the capacitor is electrically connected to the third wiring. - View Dependent Claims (14, 15, 16, 17)
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Specification