Buried channel deeply depleted channel transistor

• US 9,478,571 B1
• Filed: 05/23/2014
• Issued: 10/25/2016
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Bakhishev, Teymur, Wang, Lingquan, Zhao, Dalong, Ranade, Pushkar, Thompson, Scott E.
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US14/286,063
• Time in Patent Office: 886 Days
• Field of Search: 257/402, 257/403, 257/E29.27, 438/217, 438/289
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having one or more first device regions of a first conductivity type;

adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type at the surface of the semiconductor substrate and having an effective doping density that is substantially higher than an effective doping density of the first device regions;

forming a substantially undoped layer of semiconducting material at least over the at least one of the first device regions;

adding at least one second dopant of a second conductivity type into the substantially undoped layer over the at least one of the first device regions to define a channel layer above the screening layer; and

forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.

2. The method of claim 1, wherein the forming comprises depositing a blanket epitaxial layer of the semiconductor material over the surface of the semiconductor substrate.

3. The method of claim 1, wherein the adding of the at least one first dopant comprises implanting the at least one first dopant using implant conditions that result in an effective doping density of the first conductivity type in the screening region that is between about 10¹⁸ cm⁻

3 to 5×

10²⁰ cm<sup>−

3</sup>.

4. The method of claim 1, wherein the adding of the at least one second dopant comprises implanting the at least one second dopant using implant conditions that result in an effective doping density of the second conductivity type in the channel layer to be much less than an effective doping density of the source region and the drain region, by up to a few orders of magnitude or more.

5. The method of claim 1, wherein the forming of the source and drain regions comprises implanting one or more dopants of the second conductivity type in the at least one of the first device regions using implant conditions that result in the screening layer being located below and between the source and drain regions.

6. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having one or more first device regions of a first conductivity type;

adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type below the surface of the semiconductor substrate and a substantially undoped channel layer above the screening layer, the screening layer having an effective doping density that is substantially higher than an effective doping density of the first device regions;

adding at least one second dopant of a second conductivity type into the substantially undoped channel layer; and

forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.

7. The method of claim 6, wherein the adding of the at least one first dopant comprises implanting the at least one first dopant using implant conditions that result in an effective doping density of the first conductivity type in the screening layer that is between about 10¹⁸ cm⁻

3 to 5×

10²⁰ cm<sup>−

3</sup>.

8. The method of claim 6, wherein the adding of the at least one second dopant comprises implanting the at least one second dopant using implant conditions that result in an effective doping density of the second conductivity type in the channel layer to be much less than an effective doping density of the source region and the drain region, by up to a few orders of magnitude or more.

9. The method of claim 6, wherein the forming of the source and drain regions comprises implanting one or more dopants of the second conductivity type in the at least one of the first device regions using implant conditions that result in the screening layer being located below and between the source and drain regions.