Method of forming substrate contact for semiconductor on insulator (SOI) substrate

• US 9,478,600 B2
• Filed: 02/07/2014
• Issued: 10/25/2016
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wang, Geng, Booth, Roger A. Jr., Cheng, Kangguo, Ervin, Joseph, Pei, Chengwen, Todi, Ravi M.
• Primary Examiner(s): Miyoshi, Jesse Y
• Assistant Examiner(s): Kalam, Abul
• Application Number:
  US14/175,587
• Publication Number:
  US 20140154849A1
• Time in Patent Office: 991 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Claims

1. A method of forming a semiconductor device comprising:

providing an upper semiconductor layer on a dielectric layer, wherein said dielectric layer is present on a base semiconductor layer;

forming an etch mask on a surface of said upper semiconductor layer, wherein said etch mask comprises a contact opening having a first width and a capacitor opening having a second width, wherein said first width is of a dimension that is greater than 2 times said value of said second width;

etching a contact trench and a capacitor trench into contact with said base semiconductor layer;

forming a conformal dielectric layer on said contact trench and said capacitor trench;

recessing said conformal dielectric layer within said contact trench and said capacitor trench with an anisotropic etch, wherein a first remaining portion of said conformal dielectric layer that is present in said contact trench is below said upper surface of base semiconductor layer to expose a sidewall portion of said base semiconductor layer within said contact trench, and a second remaining portion of said conformal dielectric layer that is present in said capacitor trench is present on an entirety of said sidewalls and base portions of said capacitor trench that is present in said base semiconductor layer; and

filling said contact trench and said capacitor trench with a conductive material.

2. The method of claim 1, wherein said forming of said etch mask comprises depositing at least one pad nitride layer on said upper semiconductor layer, forming a photoresist mask atop said at least one pad nitride layer, patterning said photoresist mask, and etching said at least one pad nitride layer to provide said etch mask.

3. The method of claim 1, further comprising forming a buried plate in said base semiconductor layer adjacent to said contact trench and the capacitor trench, wherein said forming said buried plate is performed prior to filling said contact trench and said capacitor trench with said conductive material.

4. The method of claim 1, wherein said first width ranges from 0.1 microns to 0.5 microns and said second width ranges from 0.03 microns to 0.2 microns.

5. The method of claim 1, wherein said forming said conformal dielectric layer conformal dielectric layer comprises a plasma enhanced chemical vapor deposition (PECVD) process.

6. The method of claim 1, wherein prior to said recessing said conformal dielectric layer said method further comprises forming a conformal metal layer on said conformal dielectric layer present in said contact trench and said capacitor trench, and filling said contact trench and said capacitor trench with a doped semiconductor material, wherein said doped semiconductor material has a surface in contact with a surface of said conformal metal layer.

7. The method of claim 6, wherein said anisotropic etch that recesses said conformal dielectric layer further recesses said conformal metal layer and said doped semiconductor material.

8. The method of claim 7, wherein said recessing of said conformal dielectric layer, said conformal metal layer and said doped semiconductor material comprises reactive ion etching, wherein a greater first width than said second width provides that said reactive ion etching removes said conformal dielectric layer, said conformal metal layer and said doped semiconductor material present in said contact trench at a greater rate than said conformal dielectric layer, said conformal metal layer and said doped semiconductor material that is present in said capacitor trench.

9. The method of claim 8, wherein said conformal dielectric layer comprises silicon nitride, said conformal metal layer comprises titanium nitride (TiN), and said doped semiconductor material comprises n-type doped polysilicon.

10. The method of claim 9, wherein said reactive ion etch comprises halogen containing gases.

11. The method of claim 1, wherein said etching said contact trench and said capacitor trench comprises a multi-stage etching process, said multi-stage etching processing comprises:

a first etching stage which removes exposed portions of said upper semiconductor layer selective to said dielectric layer;

a second etching stage which removes exposed portions of said dielectric layer; and

a third etching stage which removes exposed portions of said base semiconductor layer.

12. The method of claim 11, wherein said contact trench and said capacitor trench are etched simultaneously.

13. The method of claim 1, wherein said filling said contact trench and said capacitor trench with said conductive material comprises a physical vapor deposition process and planarization.

14. The method of claim 1, wherein said physical vapor deposition comprises plating or sputter.

15. The method of claim 13, wherein an upper surface of said conductive material is coplanar with an upper surface of upper semiconductor layer.

16. The method of claim 1, further comprising forming at least one access transistor on said upper semiconductor layer, wherein said forming said at least one access transistor is performed after filling said contact trench and said capacitor trench with said conductive material.

17. The method of claim 1, wherein said forming said at least one access transistor comprises forming a source region and a drain region within different portions of said upper semiconductor layer, and wherein one of said source region or said drain region is in electrical communication with said conductive material.

18. The method of claim 1, further comprising forming a contact pad on an exposed surface of said conductive material.

19. The method of claim 18, further comprising a metal semiconductor alloy layer on an exposed surface of said contact pad.