Device and method for fabricating thin semiconductor channel and buried strain memorization layer

• US 9,478,658 B2
• Filed: 05/20/2015
• Issued: 10/25/2016
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Khakifirooz, Ali, Cheng, Kangguo, Doris, Bruce B., Kulkarni, Pranita, Shahidi, Ghavam G.
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): JONES, ERIC W
• Application Number:
  US14/717,551
• Publication Number:
  US 20150255603A1
• Time in Patent Office: 524 Days
• Field of Search: 257/66, 257/288
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Claims

1. A semiconductor device, comprising:

a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer;

a gate structure for a transistor device formed on the first semiconductor layer; and

a memorization layer formed from a recrystallized material of the second semiconductor layer such that stress induced in the recrystallized material induces stress to a device channel formed below the gate structure in the first semiconductor layer,

wherein the recrystallized material is doped with implantation ions, the implantation ions including Xe, Ar, N or combination thereof, and

wherein the first semiconductor layer and the dielectric layer are not doped with the implantation ions.

2. The device as recited in claim 1, wherein the semiconductor device includes n-type and p-type polarity devices and the semiconductor device includes only one of n-type polarity devices and p-type polarity device having a stressed channel in the first semiconductor layer from the memorization layer.

3. The device as recited in claim 1, wherein the semiconductor device includes n-type and p-type polarity devices and the n-type polarity devices have a different amount of stress than the p-type polarity devices in a stressed channel in the first semiconductor layer.

4. The device as recited in claim 1, wherein the substrate is a semiconductor-on-insulator (SOI) wafer.

5. The device as recited in claim 1, wherein the dopants are present in a dose ranging from 2×

10¹³/cm² to 8×

10¹⁵/cm².

6. The device as recited in claim 1, wherein the stress in the device channel is tensile.

7. The device as recited in claim 6, wherein the device is an NFET.

8. The device as recited in claim 1, wherein the stress in the device channel is compressive.

9. The device as recited in claim 8, wherein the device is a PFET.

10. A semiconductor device, comprising:

a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer;

a gate structure for a transistor device formed on the first semiconductor layer; and

a memorization layer formed from a recrystallized material of the second semiconductor layer such that stress induced in the recrystallized material induces a tensile stress to a device channel formed below the gate structure in the first semiconductor layer,

wherein the semiconductor device is an NFET,

wherein the recrystallized material is doped with implantation ions, the implantation ions including Xe, Ar, N or combination thereof, and

wherein the first semiconductor layer and the dielectric layer are not doped with the implantation ions.

11. The semiconductor device of claim 10, wherein the dopants are present in a dose ranging from 2×

10¹³/cm² to 8×

10¹⁵/cm².

12. A semiconductor device, comprising:

a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer;

a gate structure for a transistor device formed on the first semiconductor layer; and

a memorization layer formed from a recrystallized material of the second semiconductor layer such that stress induced in the recrystallized material induces a compressive stress to a device channel formed below the gate structure in the first semiconductor layer,

wherein the semiconductor device is a PFET,

wherein the recrystallized material is doped with implantation ions, the implantation ions including Xe, Ar, N or combination thereof, and

wherein the first semiconductor layer and the dielectric layer are not doped with the implantation ions.

13. The semiconductor device of claim 12, wherein the dopants are present in a dose ranging from 2×

10¹³/cm² to 8×

10¹⁵/cm².