Low-power activation circuit with motion sensor

• US 9,479,164 B2
• Filed: 07/01/2014
• Issued: 10/25/2016
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Motz, Mario
• Primary Examiner(s): PATIDAR, JAY M
• Application Number:
  US14/320,718
• Publication Number:
  US 20140312934A1
• Time in Patent Office: 847 Days
• Field of Search: 32420711-20726, 324173-174
• US Class Current: 1/1
• CPC Class Codes: G01D 5/142 using Hall-effect devices measuring magnetic variables using Hall-effect or other galvanomagnetic devices G01R33/06
• CPC Class Codes: G01P 13/00 Indicating or recording presence, absence, or direction, of movement electric switches H01H; counting moving objects G06M7/00
• CPC Class Codes: G01P 3/489 Digital circuits therefor
• CPC Class Codes: G01R 17/02 Arrangements in which the value to be measured is automatically compared with a reference value
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 33/0029 Treating the measured signals, e.g. removing offset or noise
• CPC Class Codes: H03K 17/94 characterised by the way in which the control signals are generated
• CPC Class Codes: H03K 17/9517 using galvanomagnetic devices
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

One embodiment of the present invention relates to a method and apparatus to perform a low power activation of a system by measuring the slope of a digital signal corresponding to a motion sensor measurement value. In one embodiment, a low power activation circuit is coupled to magnetic motion sensor configured to output a magnetic signal proportional to a measured magnetic field. The low power activation circuit may comprise a digital tracking circuit configured to provide a digital signal that tracks the magnetic field and a difference detector configured to detect a difference between a current digital signal and a prior digital signal stored in a digital storage means. If the detected difference is larger than a digital reference level, an activation signal is output to awaken a system from a sleep mode.

Claims

1. An activation circuit, comprising:

a magnetic sensor configured to output a signal proportional to a measured magnetic quantity;

a digital difference detection circuit configured to convert the measured magnetic quantity to a digital signal, wherein the digital difference detection circuit is configured to operate according to a low power phase and an operating phase;

wherein in the operating phase the digital difference detection circuit compares a current digital signal to selected ones of previous digital signals stored in a digital storage element, to detect at least one difference in digital signals;

wherein if the at least one difference in the digital signals is larger than a digital reference level, the digital difference detection circuit causes an activation signal generator to generate an activation signal that activates a system from the low power phase; and

wherein the digital difference detection circuit is configured to detect an upward change or a downward change for a time, and if the time is greater than the digital reference level the activation signal generator generates the activation signal.

2. The activation circuit of claim 1, wherein the digital difference detection circuit, comprises:

an analog-to-digital converter configured to track the measured magnetic quantity by converting the signal to the digital signal which corresponds to the measured magnetic quantity;

a difference detector configured to measure the at least one difference in the digital signals and to output a difference signal comprising information concerning a magnitude of the at least one difference in the digital signals.

3. The activation circuit of claim 2, wherein after the system is activated, the digital signal output from the analog-to-digital converter or the difference signal output of the difference detector is outputable to the system.

4. The activation circuit of claim 2, wherein after the system is activated, the analog-to-digital converter is configured to change from a step-by-step tracking mode to a successive operation mode or an adaptive tracking mode.

5. The activation circuit of claim 1, wherein the digital difference detection circuit comprises:

a comparator configured to receive a differential input voltage output from the magnetic sensor and to generate a comparator signal;

a digital logic element coupled to an output of the comparator; and

a current steering digital to analog converter coupled to the comparator and configured to compensate the differential input voltage of the comparator.

6. The activation circuit of claim 2, further comprising:

an offset compensation circuit located between the analog-to-digital converter and the difference detector, and configured to remove an offset of the signal such that the difference detector compares a first offset compensated signal with at least a second offset compensated signal.

7. The activation circuit of claim 6, further comprising:

one or more switches disposed between the magnetic sensor and the analog-to-digital converter, the one or more switches configured to be selectively operated at a chopping frequency that enables a current spinning method to provide a first chopping signal comprising an offset and a second chopping signal comprising the offset,

wherein the digital difference detection circuit is configured to cancel the offset by building a modulated digital signal from the first and second chopping signals.

8. The activation circuit of claim 6, further comprising:

a low power oscillator configured to operate as a clock for the activation circuit in the low power phase; and

a fast oscillator configured to drive the analog-to-digital converter, the offset compensation circuit or the difference detector in the operating phase.

9. The activation circuit of claim 1, further comprising one or more high voltage protection circuits configured to reject high voltages or reverse battery voltages.

10. The activation circuit of claim 9, wherein the one or more high voltage protection circuits respectively comprise a depletion-MOS transistor or a JFET transistor that provides a low-voltage supply voltage at minimum supply current for a low power oscillator, a latch or the digital storage element.

11. The activation circuit of claim 1, wherein the digital reference level is provided to the activation circuit from an apparatus external to the activation circuit.

12. The activation circuit according to claim 1, wherein the activation signal is adapted to awaken a system receiving the activation signal from a sleep mode, or wherein in the low power phase, digital signals are stored.

13. The activation circuit of claim 1, further comprising:

an analog-to-digital converter configured to track the signal by converting the signal to a digital signal which corresponds to the measured magnetic quantity;

wherein during the operating phase, which has a first current consumption, the analog-to-digital converter tracks the signal and the digital difference detection circuit measures the difference between the current digital signal and the selected ones of the previous digital signals; and

wherein during the low power phase the analog-to-digital converter or the digital difference detection circuit have a second current consumption lower than the first current consumption.