Measuring setup and hold times using a virtual delay
First Claim
1. A method comprising:
- providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay;
providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and
providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time, hold time, or a combination thereof of a device under test are generated based on a signal of the output of the first digital frequency divider and a signal of the output of the flip-flop, respectively.
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Accused Products
Abstract
Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.
4 Citations
20 Claims
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1. A method comprising:
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providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time, hold time, or a combination thereof of a device under test are generated based on a signal of the output of the first digital frequency divider and a signal of the output of the flip-flop, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 15)
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10. An apparatus comprising:
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a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time, hold time, or a combination thereof of a device under test are generated based on a signal of the output of the first digital frequency divider and a signal of the output of the flip-flop, respectively. - View Dependent Claims (11, 12, 13, 14)
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16. An apparatus comprising:
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a device under test having a data input, clock input, and output; and a test circuit having an input coupled to the output of the device under test and first and second outputs coupled the data and clock inputs, respectively, the test circuit comprising; a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider, wherein a data signal and clock signal for measuring a set-up time, hold time, or a combination thereof of the device under test are generated on the first and second outputs of the test circuit and the data and clock signals are based on a signal of the output of the first digital frequency divider and a signal of the output of the flip-flop, respectively. - View Dependent Claims (17, 18, 19, 20)
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Specification