Reduced frequency backwards clock for isolated sigma-delta modulators

• US 9,479,325 B1
• Filed: 12/26/2013
• Issued: 10/25/2016
• Est. Priority Date: 04/12/2013
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Strode, Jonathan R., Hematy, Arman
• Primary Examiner(s): WOLDEKIDAN, HIBRET ASNAKE
• Application Number:
  US14/140,743
• Time in Patent Office: 1,034 Days
• Field of Search: 398135-139, 398/154, 398/155, 398162-164
• US Class Current: 1/1
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H04B 10/00 Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A system includes a divider on a first side of electrically isolated circuitry for receiving a clock signal having a characteristic frequency and dividing the clock signal by a characteristic value. The system also includes an optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry. The system further includes a phase-locked loop on the second side of the electrically isolated circuitry. The phase-locked loop is coupled with the optical link and configured to receive the divided clock signal from the optical link and generate a second signal at a multiple of a characteristic frequency of the divided clock signal so that the second signal comprises the characteristic frequency of the clock signal received by the divider circuitry.

Claims

1. A system comprising:

a divider on a first side of electrically isolated circuitry for receiving a clock signal having a characteristic frequency and dividing the clock signal by a characteristic value;

an optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry; and

phase-locked loop circuitry on the second side of the electrically isolated circuitry, the phase-locked loop circuitry coupled with the optical link and configured to receive the divided clock signal from the optical link and generate a second signal at a multiple of a characteristic frequency of the divided clock signal so that the second signal comprises the characteristic frequency of the clock signal received by the divider circuitry, wherein the phase-locked loop circuitry is disposed on a first integrated circuit chip, the optical link is disposed on a second integrated circuit chip, and the divider is disposed on a third integrated circuit chip, the phase-locked loop circuitry including a phase detector and filter and a voltage controlled oscillator, the voltage controlled oscillator directly coupled to a sigma-delta modulator, the voltage controlled oscillator supplying the second signal to the sigma-delta modulator and a divided feedback signal to the phase detector and filter.

2. The system as recited in claim 1, further comprising a second optical link for transmitting signals from the second side of the electrically isolated circuitry to the first side of the electrically isolated circuitry.

3. The system as recited in claim 2, wherein the speed of the second optical link is greater than the speed of the optical link.

4. The system as recited in claim 1, wherein the first side of the electrically isolated circuitry is configured to operate at a higher voltage than the second side of the electrically isolated circuitry.

5. The system as recited in claim 1, wherein the first integrated circuit chip, the second integrated circuit chip, and the third integrated circuit chip are included in a chip package.

6. The system as recited in claim 1, wherein the clock signal comprises an external master clock signal.

7. A system comprising:

a divider on a first side of electrically isolated circuitry for receiving a clock signal having a characteristic frequency and dividing the clock signal by a characteristic value;

a first optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry;

a second optical link for transmitting signals from the second side of the electrically isolated circuitry to the first side of the electrically isolated circuitry; and

phase-locked loop circuitry on the second side of the electrically isolated circuitry, the phaselocked loop circuitry coupled with the first optical link and configured to receive the divided clock signal from the first optical link and generate a second signal at a multiple of a characteristic frequency of the divided clock signal so that the second signal comprises the characteristic frequency of the clock signal received by the divider circuitry, wherein the phase-locked loop circuitry is disposed on a first integrated circuit chip, the first optical link and the second optical link are disposed on a second integrated circuit chip, and the divider is disposed on a third integrated circuit chip, the phase-locked loop circuitry including a phase detector and filter and a voltage controlled oscillator, the voltage controlled oscillator directly coupled to a sigma-delta modulator, the voltage controlled oscillator supplying the second signal to the sigma-delta modulator and a divided feedback signal to the phase detector and filter.

8. The system as recited in claim 7, wherein the speed of the second optical link is greater than the speed of the first optical link.

9. The system as recited in claim 7, wherein the first side of the electrically isolated circuitry is configured to operate at a higher voltage than the second side of the electrically isolated circuitry.

10. The system as recited in claim 7, wherein the first integrated circuit chip, the second integrated circuit chip, and the third integrated circuit chip are included in a chip package.

11. The system as recited in claim 7, wherein the clock signal comprises an external master clock signal.

12. A chip package comprising:

a first integrated circuit chip comprising a divider on a first side of electrically isolated circuitry for receiving a clock signal having a characteristic frequency and dividing the clock signal by a characteristic value;

a second integrated circuit chip comprising an optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry; and

a third integrated circuit chip comprising phase-locked loop circuitry on the second side of the electrically isolated circuitry, the phase-locked loop circuitry coupled with the optical link and configured to receive the divided clock signal from the optical link and generate a second signal at a multiple of a characteristic frequency of the divided clock signal so that the second signal comprises the characteristic frequency of the clock signal received by the divider circuitry, the phase-locked loop circuitry including a phase detector and filter and a voltage controlled oscillator, the voltage controlled oscillator directly coupled to a sigma-delta modulator, the voltage controlled oscillator supplying the second signal to the sigma-delta modulator and a divided feedback signal to the phase detector and filter.

13. The chip package as recited in claim 12, further comprising a second optical link for transmitting signals from the second side of the electrically isolated circuitry to the first side of the electrically isolated circuitry.

14. The chip package as recited in claim 12, wherein the speed of the second optical link is greater than the speed of the optical link.

15. The chip package as recited in claim 12, wherein the first side of the electrically isolated circuitry is configured to operate at a higher voltage than the second side of the electrically isolated circuitry.