Vector signaling codes with high pin-efficiency for chip-to-chip communication and storage

• US 9,479,369 B1
• Filed: 02/02/2015
• Issued: 10/25/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): Joseph, Jaison
• Application Number:
  US14/612,252
• Time in Patent Office: 631 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03789 Codes therefore
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/4921 using quadrature encoding, e.g. carrierless amplitude-phase coding

Abstract

An alternative type of vector signaling codes having increased pin-efficiency normal vector signaling codes is described. Receivers for these Permutation Modulation codes of Type II use comparators requiring at most one fixed reference voltage. The resulting systems can allow for a better immunity to ISI-noise than those using conventional multilevel signaling such as PAM-X. These codes are also particularly advantageous for storage and recovery of information in memory, as in a DRAM.

Claims

1. A method comprising:

obtaining a Permutation Modulation Variant II code (PM II code) of length N;

determining an orthogonal matrix M of format (N+1)×

(N+1), wherein the sum of all the columns in the matrix M is 0, except for one;

transforming the PM-II code using the orthogonal matrix M to obtain a reference-less, balanced vector signaling code, wherein the reference-less, balanced vector signaling code is normalized such that each element is between 1 and −

1; and

transmitting the reference-less, balanced vector signaling code.

2. The method of claim 1, wherein the pin efficiency of the PM-II code is at least 1.5.

3. The method of claim 1, wherein each codeword of the PM-II code has at least 2 elements.

4. The method of claim 1, wherein the reference-less, balanced vector signaling code has an equal inter-symbol interference USD ration equal to the PM-II code.

5. The method of claim 1, wherein the reference-less, balanced vector signaling code is at least ternary.

6. The method of claim 1, further comprising receiving, at a set of common-mode resistant multi-input comparators (MICs), N+1 elements of a codeword, and responsively generating a set of comparator outputs.

7. The method of claim 6, wherein the set of common-mode resistant MICs comprises N+1 MICs.

8. The method of claim 7, wherein the set of common-mode resistant MICs comprises fewer than N+1 MICs.

9. The method of claim 6, wherein each MIC receives the N+1 elements of the codeword.

10. The method of claim 6, wherein at least two of the MICs are mutually orthogonal.

11. An apparatus comprising:

an encoder configured to obtain a Permutation Modulation Variant II code (PM-II code) of length N, to determining an orthogonal matrix M of format (N+1)×

(N+1), wherein the sum of all the columns in the matrix M is 0, except for one, and to transform the PM-II code using the orthogonal matrix M to obtain a reference-less, balanced vector signaling code, wherein the reference-less, balanced vector signaling code is normalized such that each element is between 1 and −

1; and

a transmit driver configured to transmit the reference-less, balanced vector signaling code over a multi-wire bus.

12. The apparatus of claim 11, wherein the pin efficiency of the PM-II code is at least 1.5.

13. The apparatus of claim 11, wherein each codeword of the PM-II code has at least 2 elements.

14. The apparatus of claim 11, wherein the reference-less, balanced vector signaling code has an equal inter-symbol interference USD ration equal to the PM-II code.

15. The apparatus of claim 11, wherein the reference-less, balanced vector signaling code is at least ternary.

16. The apparatus of claim 11, further comprising a set of common-mode resistant multi-input comparators (MICs) configured to receive N+1 elements of a codeword and to generate a set of comparator outputs.

17. The apparatus of claim 16, wherein the set of common-mode resistant MICs comprises N+1 MICs.

18. The apparatus of claim 17, wherein the set of common-mode resistant MICs comprises fewer than N+1 MICs.

19. The apparatus of claim 16, wherein each MIC receives the N+1 elements of the codeword.

20. The apparatus of claim 16, wherein at least two of the MICs are mutually orthogonal.