Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices

• US 9,481,566 B2
• Filed: 07/08/2013
• Issued: 11/01/2016
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Sadaka, Mariam, Aspar, Bernard, Blanchard, Chrystelle Lagahe
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Yasmeen, Nishath
• Application Number:
  US14/416,825
• Publication Number:
  US 20150191344A1
• Time in Patent Office: 1,212 Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H03H 9/10 Mounting in enclosures constructional combinations of enclosure with electromechanical and other electronic elements H03H9/0538

Abstract

Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.

Claims

1. A method of forming a semiconductor device comprising an integrated circuit and a MEMS device operatively coupled with the integrated circuit, comprising:

forming an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate;

fabricating at least a portion of an integrated circuit on the first major surface of the substrate; and

providing a MEMS device on the second major surface of the substrate and operatively coupling the MEMS device with the integrated circuit using the at least one electrically conductive via, wherein providing the MEMS device on the second major surface of the substrate comprises integrally forming at least a portion of the MEMS device on the second major surface of the substrate, integrally forming the at least a portion of the MEMS device on the second major surface of the substrate comprising;

forming at least one transducer cavity recess in the second major surface of the substrate; and

bonding an SOI-type structure to the second major surface of the substrate, the SOI-type substrate including a relatively thin layer of material bonded to a relatively thick volume of bulk material with an intermediate material between the relatively thin layer of material and the relatively thick volume of bulk material;

removing a portion of the SOI-type structure and leaving the thin layer of material bonded to the second major surface of the substrate; and

configuring a portion of the thin layer of material over the transducer cavity recess to comprise at least a portion of a transducer of the MEMS device; and

further comprising thinning the substrate after fabricating the at least a portion of the integrated circuit on the first major surface of the substrate and before providing the MEMS device on the second major surface of the substrate.

2. The method of claim 1, wherein fabricating the at least a portion of the integrated circuit on the first major surface of the substrate comprises forming at least one transistor on the first major surface of the substrate.

3. The method of claim 2, wherein fabricating the at least a portion of the integrated circuit on the first major surface of the substrate further comprises forming at least one electrically conductive feature over the first major surface of the substrate, the at least one electrically conductive feature electrically coupled with the electrically conductive via.

4. The method of claim 1, further comprising selecting the MEMS device to comprise at least one of a resonator and a sensor.

5. The method of claim 4, further comprising selecting the MEMS device to comprise at least one of a plate acoustic wave resonator, a flexural mode resonator, a bulk acoustic wave (BAW) resonator, a surface acoustic wave (SAW) resonator, and a film bulk acoustic resonator (FBAR).

6. The method of claim 1, wherein fabricating the at least a portion of the integrated circuit on the first major surface of the substrate further comprises forming at least one electrically conductive feature over the first major surface of the substrate, the at least one electrically conductive feature electrically coupled with the electrically conductive via.

7. The method of claim 1, wherein thinning the substrate comprises thinning the substrate to an average thickness of about two hundred fifty microns (250 um) or less.

8. The method of claim 7, wherein thinning the substrate comprises thinning the substrate to an average thickness of about two hundred microns (200 μ

m) or less.

9. The method of claim 8, wherein thinning the substrate comprises thinning the substrate to an average thickness of about one hundred microns (100 μ

m) or less.

10. The method of claim 1, wherein the relatively thin layer of material of the SOI-type structure comprises at least one of a piezoelectric material, a semiconductor material, a ceramic material, or a metal material;

wherein the piezoelectric materials includes, for example, quartz, AlPO₄, GaPO₄, BaTiO₃, lead zirconate titanate (PZT), zinc oxide, or aluminum nitride.

11. The method of claim 1, wherein the relatively thin layer of material of the SOI-type structure comprises a semiconductor material.

12. The method of claim 11, wherein the semiconductor material comprises at least one of silicon, germanium, or a III-V semiconductor material.

13. The method of claim 1, wherein the relatively thin layer of material of the SOT-type structure has an average layer thickness between about five nanometers (5 nm) and about five hundred microns (500 μ

m).

14. The method of claim 13, wherein the relatively thin layer of material of the SOI-type structure has an average layer thickness between about five nanometers (5 nm) and about one hundred microns (100 μ

m).

15. The method of claim 14, wherein the relatively thin layer of material of the SOI-type structure has an average layer thickness between about five nanometers (5 nm) and about ten microns (10 μ

m).

16. The method of claim 1, wherein bonding an SOI-type structure to the second major surface of the substrate comprises using a direct bonding process to bond the SOI-type structure to the second major surface of the substrate.

17. The method of claim 1, further comprising forming trenches and/or holes in or through the relatively thin layer of material of the SOI-type structure proximate the at least one transducer cavity recess.

18. The method of claim 1, further comprising establishing electrical interconnection between the transducer and the electrically conductive via.

19. The method of claim 1, further comprising providing a cap structure over the relatively thin layer of material of the SOI-type structure, the cap structure comprising another transducer cavity recess located and configured to be disposed adjacent the transducer on a side thereof opposite the at least one transducer cavity recess formed in the substrate.