Memory system and control method thereof

• US 9,483,192 B2
• Filed: 10/26/2015
• Issued: 11/01/2016
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kitsunai, Kazuya, Kanno, Shinichi, Yano, Hirokuni, Hida, Toshikatsu, Yano, Junji
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US14/923,128
• Publication Number:
  US 20160041767A1
• Time in Patent Office: 372 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Claims

1. A memory system comprising:

a controller which includes a host interface circuit and a NAND interface circuit; and

a NAND flash memory including a plurality of blocks as data erase units, the block including free blocks, the NAND flash memory storing management information for each of the block,

wherein

the host interface circuit receives first data and a write command from the host,

the controller selects a block whose erase count is lowest and does not contain valid data, based on the management information,

the controller writes the first data into the selected block via the NAND interface circuit,

the controller changes the management information to indicate the selected block stores valid data, and

the controller replaces a less frequently used block with a free block having an erase count higher than the less frequently used block.

2. The memory system according to claim 1, wherein the management information includes:

first information indicating an erase count, and

second information indicating if a block stores valid data.

3. The memory system according to claim 2, comprising the memory system being configured to perform a first mode and a second mode where, in the second mode:

the controller selects a first block whose erase count is a first number and which contains second data that is valid, based on the management information,

the controller selects a second block whose erase count is a second number larger than the first number and which does not contain valid data, based on the management information,

the controller writes the second data into the second block, and

the controller changes the management information to indicate the first block does not store valid data and the second block does store valid data.

4. The memory system according to claim 2, further comprising:

a RAM configured to store the management information.

5. The memory system according to claim 2, comprising:

the management information being configured to be stored in a RAM and the NAND flash memory, and to be updated in the RAM.

6. The memory system according to claim 2, wherein the management information is registered with an erase time of the block.

7. The memory system according to claim 1, further comprising:

an error check and correction circuit.

8. The memory system according to claim 1, further comprising:

a power source circuit being configured to be supplied with an external power source voltage and to generate a plurality of internal power source voltages by use of the external power source voltage.

9. The memory system according to claim 1, wherein the memory system is configured to be detachable from the host.

10. The memory system according to claim 1, further comprising:

a second NAND flash memory, a third NAND flash memory, and a fourth NAND flash memory.

11. The memory system according to claim 1, wherein the controller selects the block by referring to an erase time of the block.

12. A memory system comprising:

a controller which includes a host interface circuit and a NAND interface circuit; and

a NAND flash memory including a plurality of blocks as data erase units, the blocks including free blocks, the NAND flash memory storing management information for each of the block,

wherein the controller is configured to execute first and second wear leveling processes, in the first process

the host interface circuit receives first data and a write command from the host;

the controller selects a block whose erase count is lowest and does not contain valid data, based on the management information;

the controller writes the first data into the selected block via the NAND interface circuit; and

the controller changes the management information to indicate the selected block stores valid data, and

the second process includes replacing a less frequently used block with a free block having an erase count higher than the less frequently used block.

13. The memory system according to claim 12, wherein the management information includes:

first information indicating an erase count, and

second information indicating whether a block stores valid data.

14. The memory system according to claim 13, wherein, in the second process:

the controller selects a first block whose erase count is a first number and which contains second data that is valid, based on the management information,

the controller selects a second block whose erase count is a second number larger than the first number and which does not contain valid data, based on the management information,

the controller writes the second data into the second block, and

the controller changes the management information to indicate the first block does not store valid data and the second block does store valid data.

15. The memory system according to claim 13, further comprising:

a RAM configured to store the management information.

16. The memory system according to claim 13, wherein the management information is configured to be stored in a RAM and the NAND flash memory, and to be updated in the RAM.

17. The memory system according to claim 12, further comprising:

an error check and correction circuit.

18. The memory system according to claim 12, further comprising:

a power source circuit configured to be supplied with external power source voltage and to generate a plurality of internal power source voltages by use of the external power source voltage.

19. The memory system according to claim 12, wherein the memory system is configured to be detachable from the host.

20. The memory system according to claim 12, further comprising:

a second NAND flash memory, a third NAND flash memory, and a fourth NAND flash memory.

21. The memory system according to claim 12, wherein the management information is registered with an erase time of the block.

22. the memory system according to claim 12, wherein the controller selects the block by referring to an erase time of the block.

23. A memory system comprising:

a first nonvolatile semiconductor memory comprising at least a plurality of blocks, each of the blocks being a unit for erasure of data; and

a controller comprising,

a host interface circuit to receive data and a command from a host, and

a memory interface circuit to interface with the first nonvolatile semiconductor memory;

the first nonvolatile semiconductor memory configured to store management information for each of the blocks, the management information including,

first information indicating an erase count, and

second information indicating whether a block stores valid data,

wherein

the first nonvolatile semiconductor memory is configured to perform a first mode and a second mode, where in the first mode;

the host interface circuit receives first data and a write command from the host,

the controller selects a block whose erase count is minimum and which does not contain valid data, based on the management information,

the controller writes the first data into the selected block via the memory interface, and

the controller changes the management information to indicate the selected block stores valid data,

where in the second mode;

the controller selects a first block whose erase count is a first number and which contains second data that is valid, based on the management information,

the controller selects a second block whose erase count is a second number larger than the first number and which does not contain valid data, based on the management information,

the controller writes the second data into the second block, and

the controller changes the management information to indicate the first block does not store valid data and the second block does store valid data.

24. The memory system according to claim 23, further comprising:

a RAM configured to store the management information.

25. The memory system according to claim 23, wherein the management information is configured to be stored in a RAM and the first nonvolatile semiconductor memory, and to be updated in the RAM.

26. The memory system according to claim 23, further comprising:

an error check and correction circuit.

27. The memory system according to claim 23, further comprising:

a power source circuit configured to be supplied with an external power source voltage and to generate a plurality of internal power source voltages by use of the external power source voltage.

28. The memory system according to claim 23, wherein the memory system is configured to be detachable from the host.

29. The memory system according to claim 23, further comprising:

a second nonvolatile semiconductor memory, a third nonvolatile semiconductor memory, and a fourth nonvolatile semiconductor memory.

30. The memory system according to claim 23, wherein the management information is registered with an erase time of the block.

31. The memory system according to claim 23, wherein the controller selects the block by referring to an erase time of the block.

32. A memory system comprising:

an interface unit which receives data from outside of the memory system;

a first nonvolatile memory including a plurality of blocks as data erase units; and

a controller which controls the first nonvolatile memory;

wherein the controller is configured to;

determine whether or not a leveling process is to be performed based on information relating to each block,

write data received from the outside into a first block to which a logical address is not allocated if it is determined that the leveling process is not to be performed, and

perform the leveling process if it is determined that the leveling process is to be performed, wherein the leveling process comprises;

reading data from a second block to which a logical address is allocated,

writing the data read from the second block into a third block of which data is erased, the number of erase counts of the second block being less than that of the third block,

releasing the logical address which is allocated to the second block, and

allocating the logical address, to the third block, which was allocated to the second block.

33. The memory system of claim 32, wherein the controller is configured to select the first block from blocks to which a logical block address is not allocated based on the information relating to each of the blocks if it is determined that the leveling process is not to be performed.

34. The memory system according to claim 32, wherein the controller is configured to determine whether or not a leveling process is to be performed based on the information relating to block.

35. The memory system according to claim 32, wherein the controller is configured to manage first information relating to blocks to which a logical block address is not allocated and second information relating to blocks to which a logical block address is allocated, and

select the second block and the third block based on the first information and the second information if it is determined that the leveling process is to be performed.

36. The memory system according to claim 32, wherein the information relating to each block comprises a degree of load concentration or the number of erase counts.

37. The memory system according to claim 32, further comprising:

a RAM configured to store management information, the management information including,

first information indicating the erase count, and

second information indicating whether a block stores valid data.

38. The memory system according to claim 37, wherein the management information is configured to be stored in a RAM and the first nonvolatile memory, and to be updated in the RAM.

39. The memory system according to claim 32, further comprising:

an error check and correction circuit.

40. The memory system according to claim 32, further comprising:

a power source circuit configured to be supplied with an external power source voltage and generates a plurality of internal power source voltages by use of the external power source voltage.

41. The memory system according to claim 32, wherein the memory system is configured to be detachable from a host.

42. The memory system according to claim 32, further comprising:

a second nonvolatile memory, a third nonvolatile memory, and a fourth nonvolatile memory.

43. The memory system according to claim 32, wherein management information is registered with an erase time of the block.

44. The memory system according to claim 32, wherein the controller selects the block by referring to an erase time of the block.

45. A memory system comprising:

a first nonvolatile semiconductor memory including a plurality of blocks as data erase units, the blocks including a first block, a second block, a third block, and a fourth block; and

a controller circuit configured to manage a relationship between a plurality of logical addressees designated by a host device and a plurality of physical addresses of the nonvolatile semiconductor memory, the logical addresses including a first logical address and a second logical address, wherein;

the controller circuit manages first information regarding erase counts of the blocks;

the controller circuit receives a request for writing first data to a first logical address from the host device;

the controller circuit performs in a response to the request;

writing the first data into the first block to which any of the logical addresses are not allocated at the time of the receiving the request;

releasing an allocation of the first logical address to the second block; and

allocating the first logical address to the first block;

the controller circuit determines whether or not a wear leveling process is to be performed; and

the controller circuit performs the wear leveling process if it is determined that the wear leveling process is to be performed including;

selecting the third block and fourth block based on at least part of the first information, an erase count of the third block being smaller than an erase count of the fourth block;

reading second data from the third block to which the second logical address is allocated;

writing the second data read from the third block into the fourth block;

releasing an allocation of the second logical address to the third block; and

allocating the second logical address to the fourth block.

46. The memory system according to claim 45, further comprising:

a RAM configured to store management information, the management information including;

the first information indicating the erase count, and

second information indicating whether a block stores valid data.

47. The memory system according to claim 46, wherein the management information is configured to be stored in a RAM and the first nonvolatile memory, and to be updated in the RAM.

48. The memory system according to claim 45, further comprising:

an error check and correction circuit.

49. The memory system according to claim 45, further comprising:

a power source circuit configured to be supplied with external power source voltage and generate a plurality of internal power source voltages by use of the external power source voltage.

50. The memory system according to claim 45, wherein the memory system is configured to be detachable from the host.

51. The memory system according to claim 45, further comprising:

a second nonvolatile memory, a third nonvolatile memory, and a fourth nonvolatile memory.

52. The memory system according to claim 45, wherein management information is registered with an erase time of the block.

53. The memory system according to claim 45, wherein the controller selects the block by referring to an erase time of the block.