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Memory system and control method thereof

  • US 9,483,192 B2
  • Filed: 10/26/2015
  • Issued: 11/01/2016
  • Est. Priority Date: 12/28/2007
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a controller which includes a host interface circuit and a NAND interface circuit; and

    a NAND flash memory including a plurality of blocks as data erase units, the block including free blocks, the NAND flash memory storing management information for each of the block,whereinthe host interface circuit receives first data and a write command from the host,the controller selects a block whose erase count is lowest and does not contain valid data, based on the management information,the controller writes the first data into the selected block via the NAND interface circuit,the controller changes the management information to indicate the selected block stores valid data, andthe controller replaces a less frequently used block with a free block having an erase count higher than the less frequently used block.

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