Hierarchical accelerator registry for optimal performance predictability in network function virtualization

• US 9,483,291 B1
• Filed: 01/29/2015
• Issued: 11/01/2016
• Est. Priority Date: 01/29/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chen, Allen, Rabi, Abdel
• Primary Examiner(s): Truong, Camquy
• Application Number:
  US14/609,306
• Time in Patent Office: 642 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 2009/4557 Distribution of virtual machine instances; Migration and load balancing
• CPC Class Codes: G06F 2009/45595 Network integration; Enabling network access in virtual machine instances
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: H04L 67/00 Network arrangements or protocols for supporting network services or applications user-to-user messaging H04L51/00; network arrangements, protocols or services for supporting real-time applications in data packet communications networks H04L65/00

Abstract

A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. To help improve performance predictability, a hierarchical accelerator registry may be maintained on the coprocessor and/or on local servers. The accelerator registry may assign different classes and speed grades to various types of available resources to help the virtualized network better predict certain task latencies. The accelerator registry may be periodically updated based on changes detected in the local storage and hardware or based on changes detected in remote networks.

Claims

1. An integrated circuit, comprising:

virtual function hardware accelerator modules that serve to improve performance for at least some virtual machine; and

a virtualization accelerator management module that maintains a hierarchical accelerator resource availability registry, wherein the hierarchical accelerator resource availability registry specifies latency information corresponding to different types of hardware acceleration resources that are available to the integrated circuit for assisting with Network Functions Virtualization (NFV), wherein the hierarchical accelerator resource availability registry is configured to assign a first speed grade to hardware acceleration resources that are presently active on the integrated circuit and to assign a second speed grade to hardware acceleration resources that can be retrieved from a local storage device, and wherein the second speed grade is different than the first speed grade.

2. The integrated circuit defined in claim 1, wherein the at least some virtual machine is running on an external host processor that is coupled to the integrated circuit.

3. The integrated circuit defined in claim 2, further comprising:

Peripheral Component Interconnect Express (PCIe) interface circuitry for communicating with the host processor.

4. The integrated circuit defined in claim 2, further comprising:

programmable logic elements that can be reconfigured to perform different custom functions.

5. The integrated circuit defined in claim 1, wherein the virtualization accelerator management module is controlled by a hypervisor running on the host processor.

6. The integrated circuit defined in claim 1, wherein the hierarchical accelerator resource availability registry is configured to assign a third speed grade to hardware acceleration resources that can be retrieved from a remote storage device, and wherein the third speed grade is different than the first and second speed grades.

7. A method of improving performance predictability for a Network Functions Virtualization (NFV) platform, comprising:

using hardware accelerator modules running on an integrated circuit to accelerate performance for at least some virtual machine;

using an accelerator management module to maintain an accelerator registry that provides predictability information for different types of hardware acceleration resources that are available to the integrated circuit for assisting with the NFV platform;

using the accelerator registry to determine the latency with which the different types of hardware acceleration resources are retrieved for the integrated circuit to assist with the NFV platform;

controlling the accelerator management module with a hypervisor running on a separate host processor that is coupled to the integrated circuit; and

synchronizing the host processor with other processing units in a local network or a remote network to identify first hardware acceleration resources that are available to the other processing units.

8. The method defined in claim 7, further comprising:

reading data from local storage devices to identify second hardware acceleration resources that are stored on the local storage devices.

9. The method defined in claim 8, further comprising:

retrieving current status information from the accelerator registry to identify third hardware acceleration resources that are currently available on the integrated circuit.

10. The method defined in claim 9, further comprising:

updating the accelerator registry based on the identified first, second, and third hardware acceleration resources.

11. The method defined in claim 9, further comprising:

in response to detecting that the integrated circuit has been at least partially reconfigured, updating the accelerator registry.

12. The method defined in claim 7, further comprising:

in response to detecting a protocol trigger that directs the host processor to synchronize with other processing units, updating the accelerator registry.

13. The method defined in claim 8, further comprising:

in response to detecting that a given file has been altered on the local storage devices, updating the accelerator registry.

14. A Network Functions Virtualization (NFV) platform, comprising:

a host processor having a hypervisor that creates and runs virtual machines; and

a coprocessor having accelerators for accelerating the performance of the virtual machines, wherein the coprocessor stores a hierarchical accelerator registry identifying different types of hardware acceleration resources that are available to the coprocessor and corresponding performance predictability considerations associated with each type of hardware acceleration resources, and wherein the hierarchical accelerator registry defines a first speed grade to hardware acceleration resources that are stored on a local network.

15. The NFV platform defined in claim 14, wherein the hierarchical accelerator registry defines a second speed grade that is faster than the first speed grade to hardware acceleration resources that are presently active on the coprocessor.

16. The NFV platform defined in claim 15, wherein the hierarchical accelerator registry defines a third speed grade that is slower than the first speed grade to hardware acceleration resources that are retrievable from a remote network.

17. The NFV platform defined in claim 16, wherein the coprocessor is at least partially reconfigured to engage the hardware acceleration resources stored on the local network or retrieved from the remote network.