Error detection/correction based memory management

• US 9,483,370 B2
• Filed: 02/18/2014
• Issued: 11/01/2016
• Est. Priority Date: 10/27/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Reche, Cory J., Nevill, Leland R., Martin, Timothy F.
• Primary Examiner(s): Duncan, Marc
• Application Number:
  US14/182,963
• Publication Number:
  US 20140164824A1
• Time in Patent Office: 987 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/2053 where persistent mass storage functionality or persistent mass storage control functionality is redundant error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Claims

1. An apparatus, comprising:

an array of memory cells; and

a controller configured to control;

performing a read operation on a group of memory cells of the array of memory cells;

responsive to determining that the read operation results in an uncorrectable error, determining whether to retire the group of memory cells based, at least partially, on a status of an indicator corresponding to the group of memory cells, wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith; and

storing the indicator in the array of memory cells; and

wherein the controller is configured to control tracking a ratio of total uncorrectable errors to total data throughput associated with the array of memory cells.

2. The apparatus of claim 1, wherein the group of memory cells is a block of memory cells configured to be erased together.

3. The apparatus of claim 1, wherein the controller is configured to control retiring the group of memory cells if the status of the indicator indicates that a threshold number of uncorrectable errors associated with the group of memory cells has been reached.

4. The apparatus of claim 1, wherein the controller is configured to control retiring the group of memory cells if the status of the indicator indicates the group of memory cells has a previous uncorrectable error associated therewith.

5. A method, comprising:

performing a read operation on a group of memory cells of an array of memory cells; and

responsive to the read operation resulting in an uncorrectable error, determining whether to retire the group of memory cells based on a status of an indicator corresponding to the group of memory cells;

wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith;

wherein the indicator is a counter, and wherein determining whether to retire the group of memory cells based on the status of the counter comprises determining whether the group of memory cells has experienced a threshold number of uncorrectable errors; and

adjusting the threshold number of uncorrectable errors used to determine whether to retire the group of memory cells.

6. The method of claim 5, including performing the read operation via control circuitry coupled to the array of memory cells, wherein the indicator is not stored within the control circuitry.

7. The method of claim 5, wherein the threshold number of uncorrectable errors is at least three.

8. The method of claim 5, wherein adjusting the threshold number of uncorrectable errors used to determine whether to retire the group of memory cells includes reducing the threshold number of uncorrectable errors based, at least partially, on an age of the array of memory cells.

9. The method of claim 5, wherein adjusting the threshold number of uncorrectable errors used to determine whether to retire the group of memory cells includes reducing the threshold number of uncorrectable errors based, at least partially, on a number of program/erase cycles performed on the group of memory cells.

10. An apparatus, comprising:

a host;

a number of memory cell arrays; and

control circuitry coupled to the number of memory cell arrays and configured to;

perform read operations on groups of memory cells corresponding to the number of memory cell arrays;

determine whether a read operation performed on a particular group of memory cells results in an uncorrectable error; and

in response to determining that the read operation results in an uncorrectable error, determine whether to retire the particular group of memory cells based, at least partially, on a status of an indicator, wherein the status of the indicator indicates whether the particular group of memory cells has experienced a previous uncorrectable error;

wherein the indicator is stored within a particular memory cell array; and

wherein the controller is configured to adjust a threshold number of uncorrectable errors associated with the particular group of memory cells based, at least partially, on at least one of;

an age of the memory cell array to which the particular group of memory cells corresponds; and

an amount of program/erase cycles performed on the particular group of memory cells.

11. The apparatus of claim 10, wherein the particular group of memory cells is a block of memory cells.

12. The apparatus of claim 10, wherein the control circuitry is configured to determine whether the particular group of memory cells has experienced a threshold number of uncorrectable errors, and wherein the threshold number of uncorrectable errors is variable among different groups of memory cells.

13. The apparatus of claim 10, wherein the control circuitry is configured to track a ratio of total uncorrectable errors to total data throughput associated with the number of memory cell arrays.