Error detection/correction based memory management
First Claim
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1. An apparatus, comprising:
- an array of memory cells; and
a controller configured to control;
performing a read operation on a group of memory cells of the array of memory cells;
responsive to determining that the read operation results in an uncorrectable error, determining whether to retire the group of memory cells based, at least partially, on a status of an indicator corresponding to the group of memory cells, wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith; and
storing the indicator in the array of memory cells; and
wherein the controller is configured to control tracking a ratio of total uncorrectable errors to total data throughput associated with the array of memory cells.
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Abstract
The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.
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Citations
13 Claims
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1. An apparatus, comprising:
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an array of memory cells; and a controller configured to control; performing a read operation on a group of memory cells of the array of memory cells; responsive to determining that the read operation results in an uncorrectable error, determining whether to retire the group of memory cells based, at least partially, on a status of an indicator corresponding to the group of memory cells, wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith; and storing the indicator in the array of memory cells; and wherein the controller is configured to control tracking a ratio of total uncorrectable errors to total data throughput associated with the array of memory cells. - View Dependent Claims (2, 3, 4)
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5. A method, comprising:
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performing a read operation on a group of memory cells of an array of memory cells; and responsive to the read operation resulting in an uncorrectable error, determining whether to retire the group of memory cells based on a status of an indicator corresponding to the group of memory cells; wherein the status of the indicator indicates whether the group of memory cells has a previous uncorrectable error associated therewith; wherein the indicator is a counter, and wherein determining whether to retire the group of memory cells based on the status of the counter comprises determining whether the group of memory cells has experienced a threshold number of uncorrectable errors; and adjusting the threshold number of uncorrectable errors used to determine whether to retire the group of memory cells. - View Dependent Claims (6, 7, 8, 9)
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10. An apparatus, comprising:
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a host; a number of memory cell arrays; and control circuitry coupled to the number of memory cell arrays and configured to; perform read operations on groups of memory cells corresponding to the number of memory cell arrays; determine whether a read operation performed on a particular group of memory cells results in an uncorrectable error; and in response to determining that the read operation results in an uncorrectable error, determine whether to retire the particular group of memory cells based, at least partially, on a status of an indicator, wherein the status of the indicator indicates whether the particular group of memory cells has experienced a previous uncorrectable error; wherein the indicator is stored within a particular memory cell array; and wherein the controller is configured to adjust a threshold number of uncorrectable errors associated with the particular group of memory cells based, at least partially, on at least one of; an age of the memory cell array to which the particular group of memory cells corresponds; and an amount of program/erase cycles performed on the particular group of memory cells. - View Dependent Claims (11, 12, 13)
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Specification