Nonvolatile memory devices and methods of controlling the same

• US 9,483,413 B2
• Filed: 10/24/2014
• Issued: 11/01/2016
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Erez, Elona, Dor, Avner, Landis, Shay, Kong, Jun Jin
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US14/523,159
• Publication Number:
  US 20160117256A1
• Time in Patent Office: 739 Days
• Field of Search: 711/156, 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

Claims

1. A method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages, the method comprising:

receiving a plurality of logical pages associated with a plurality of physical addresses, respectively;

storing the plurality of logical pages at the plurality of physical addresses according to a given order of logical addresses of the logical pages; and

obtaining a directory, the directory enabling access to a corresponding physical address of each stored logical page and the directory providing the corresponding physical address using the stored logical page as an input,

wherein the obtaining includes,

storing a set of incoming logical pages in a temporary memory;

storing the logical pages in an ascending order in a physical cluster; and

generating a tree structure having a plurality of nodes, each of the plurality of nodes representing a subset of the logical addresses of logical pages,

wherein the plurality of nodes include a plurality of non-leaf nodes, each of the non-leaf nodes having children nodes, an aggregation of the represented content of the children nodes of an associated non-leaf node is equal to the content of the associated non-leaf node.

2. The method of claim 1, wherein the nonvolatile memory device includes physical clusters, each physical cluster including a set of the plurality of physical pages.

3. The method of claim 1, wherein each node of the plurality of nodes includes a sequence of symbols, each symbol corresponding to a logical page.

4. The method of claim 3, wherein an order of the symbols in the non-leaf nodes determines the location of the corresponding logical pages within their corresponding children nodes.

5. The method of claim 4, wherein an order of the symbols in the leaf nodes determines a location of the corresponding logical pages within the physical cluster.

6. The method of claim 3, wherein each node comprises a second information layer, the second information layer including a set of integers, each of the set of integers is an order of one of the symbols in the non-leaf node, the one of the symbols belonging to a subset of the symbols belonging to the non-leaf node.

7. The method of claim 3, wherein the symbols are binary.

8. The method of claim 1, wherein the plurality of nodes include a plurality of leaf-nodes, the method further comprising:

decoding information associated with the plurality of leaf-nodes from the plurality of non-leaf nodes, each of the plurality of leaf-nodes corresponding to the physical cluster, the physical cluster including a set of the plurality of physical pages.

9. A memory system comprising:

a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages; and

a memory controller configured to,

receive a plurality of logical pages associated with a plurality of physical addresses, respectively;

store the plurality of logical pages at the plurality of physical addresses according to a given order of logical addresses of the logical pages; and

obtain a directory, the directory enabling access to a corresponding physical address of each stored logical page and the directory providing the corresponding physical address using the stored logical page as an input, and

wherein the memory controller is configured to,

store a set of incoming logical pages in a temporary memory;

store the logical pages in an ascending order in a physical cluster; and

generate a tree structure having a plurality of nodes, each of the plurality of nodes representing a subset of the logical addresses of logical pages,

wherein the plurality of nodes include a plurality of non-leaf nodes, each of the non-leaf nodes having children nodes, an aggregation of the represented content of the children nodes of an associated non-leaf node is equal to the content of the associated non-leaf node.

10. The memory system of claim 9, wherein the nonvolatile memory device includes physical clusters, each physical cluster including a set of the plurality of physical pages.

11. The memory system of claim 9, wherein each node of the plurality of nodes includes a sequence of symbols, each symbol corresponding to a logical page.

12. The memory system of claim 11, wherein an order of the symbols in the non-leaf nodes determines the location of the corresponding logical pages within their corresponding children nodes.

13. The memory system of claim 12, wherein an order of the symbols in the leaf nodes determines a location of the corresponding logical pages within the physical cluster.

14. The memory system of claim 11, wherein each node comprises a second information layer, the second information layer including a set of integers, each of the set of integers is an order of one of the symbols in the non-leaf node, the one of the symbols belonging to a subset of the symbols belonging to the non-leaf node.

15. The memory system of claim 11, wherein the symbols are binary.

16. The memory system of claim 9, wherein the plurality of nodes include a plurality of leaf-nodes, and the memory controller is configured to,

decode information associated with the plurality of leaf-nodes from the plurality of non-leaf nodes, each of the plurality of leaf-nodes corresponding to the physical cluster, the physical cluster including a set of the plurality of physical pages.