Apparatus and method for handling page protection faults in a computing system

• US 9,483,419 B2
• Filed: 04/25/2014
• Issued: 11/01/2016
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Murray, Simon, North, Geraint M.
• Primary Examiner(s): Cygiel, Gary W
• Application Number:
  US14/262,258
• Publication Number:
  US 20140237199A1
• Time in Patent Office: 921 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 8/52 Binary to binary
• CPC Class Codes: G06F 9/4552 Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.

Claims

1. A computing system, comprising:

a translator unit arranged to convert a subject code into a target code, the subject code comprising a reference to at least one subject memory page having associated subject page access attributes;

a target processor unit arranged to execute the target code;

a target memory associated with the target processor unit and including a page descriptor store and plurality of memory locations related to the subject memory pages, wherein address bits defining addresses of the plurality of memory locations are selected based on information in the page descriptor store according to the subject page access attributes, values of the address bits indicating a page protection condition of a corresponding subject memory page; and

wherein the translator unit is arranged to allow an attempt to access a target memory location within the plurality of memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access attributes for the associated subject memory page, and wherein the translator unit is operable to detect a page protection fault based on an attempt to access a target memory location and determine a nature of the page protection fault by examining the address bits of the respective target memory location.

2. The computing system of claim 1, wherein the translator unit is arranged to determine whether an attempt to access a target memory location within the plurality of memory locations crosses a subject page boundary, and to allow the attempt to proceed without interruption in control flow when the attempted access is within the permissions of all the subject pages involved in the attempted access.

3. The computing system of claim 1, wherein the translator unit is arranged to set up, in the target memory, a guard representation of the at least one subject memory page, said guard representation resident in an address space in the target memory that is identifiable by the target processor unit as inaccessible.

4. The computing system of claim 3, wherein the translator unit is arranged to attempt to access either the target memory location within the plurality of memory locations or to attempt to access the guard representation in accordance with the information in the page descriptor store.

5. The computing system of claim 4, wherein the target processor is arranged to generate an exception in response to an attempt to access the guard representation, and the translator unit is arranged to handle the exception with reference to a page protection fault handling unit.

6. The computing system of claim 1, wherein the plurality of memory locations in the target memory are each further associated with information inserted into the page descriptor store by the translator in order to enable the translator unit to redirect attempted accesses to shared subject pages to a corresponding shared region within the target memory.

7. The computing system of claim 1, wherein the translator unit is arranged to determine whether an attempt to access a target memory location within the plurality of memory locations crosses a subject page boundary, and to allow the attempt to proceed without interruption in control flow when the attempted access is within the permissions of the first subject page involved in the attempted access, and the permissions of the second subject page involved in the attempted access match those of the first subject page.