Opportunistic candidate path selection during physical optimization of a circuit design for an IC

• US 9,483,597 B1
• Filed: 03/24/2015
• Issued: 11/01/2016
• Est. Priority Date: 03/24/2015
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Das, Sabyasachi, Lu, Ruibing, Wang, Zhiyong
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/667,324
• Time in Patent Office: 588 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

In an example, a method of implementing a circuit design for an integrated circuit (IC) includes: placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths, and executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack. The method further includes generating a physical implementation of the circuit design for the IC based on the physical description.

Claims

1. A method of implementing a circuit design for an integrated circuit (IC), comprising:

placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths;

executing a timing analysis to determine a timing profile of the physical description, the timing profile including slack values for the plurality of paths based on a timing constraint;

optimizing the physical description by performing a plurality of iterations of;

selecting a candidate set of paths having negative slack from the plurality of paths in the physical description based on the slack values of the timing profile, the step of selecting including determining that timing of a particular path of the plurality of paths in the physical description having a most negative slack has not improved and excluding the particular path from the candidate set of paths; and

modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack;

generating a physical implementation of the circuit design for the IC based on the physical description.

2. The method of claim 1, wherein the step of optimizing comprises:

maintaining at least one queue each including paths from the candidate set of paths ordered from most negative slack to least negative slack.

3. The method of claim 2, wherein the step of maintaining comprises:

for a first iteration of the step of optimizing, creating the at least one queue after the candidate set of paths having negative slack have been selected; and

for each additional iteration of the step of optimizing, updating the at least one queue after the candidate set of paths having negative slack have been selected.

4. The method of claim 2, wherein the at least one queue comprises a plurality of queues, the paths in each of the plurality of queues being part of a respective clock group of a plurality of clock groups in the physical description.

5. The method of claim 1, further comprising:

excluding at least one additional path in a same clock group as the particular path from the candidate set of paths.

6. The method of claim 1, wherein the step of selecting comprises:

determining that timing improvement of a particular path of the plurality of paths in the physical description does not satisfy a threshold; and

excluding the particular path from the candidate set of paths.

7. The method of claim 6, further comprising:

excluding at least one additional path in a same clock group as the particular path from the candidate set of paths.

8. The method of claim 1, wherein the step of optimizing is performed for the plurality of iterations or until the candidate set of paths is empty.

9. The method of claim 8, wherein the candidate set of paths is reduced in one or more of the plurality of iterations by excluding at least one path where timing has not improved from a previous iteration or where timing improvement from a previous iteration does not satisfy a threshold.

10. The method of claim 1, further comprising:

re-executing the timing analysis to update the timing profile after one or more iterations of the step of optimizing.

11. A circuit design system, comprising:

a hardware platform comprising a central processing unit (CPU) and a memory, the memory storing a logical description of a circuit design for an integrated circuit (IC) and a timing constraint; and

a circuit design tool comprising instructions executable by the CPU in the hardware platform, the circuit design tool configured to;

place and route the logical description to generate a physical description having a plurality of paths;

execute a timing analysis to determine a timing profile of the physical description, the timing profile including slack values for the plurality of paths based on a timing constraint;

optimize the physical description by performing a plurality of iterations of;

selecting a candidate set of paths having negative slack from the plurality of paths in the physical description based on the slack values of the timing profile;

determining that timing of a particular path of the plurality of paths in the physical description having a most negative slack has not improved;

excluding the particular path from the candidate set of paths; and

modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack;

generate a physical implementation of the circuit design for the IC based on the physical description.

12. The computer system of claim 11, wherein circuit design tool is configured to:

exclude at least one additional path in a same clock group as the particular path from the candidate set of paths.

13. The computer system of claim 11, wherein circuit design tool is configured to:

determine that timing improvement of a particular path of the plurality of paths in the physical description does not satisfy a threshold; and

exclude the particular path from the candidate set of paths.

14. The computer system of claim 13, wherein circuit design tool is configured to:

exclude at least one additional path in a same clock group as the particular path from the candidate set of paths.

15. A non-transitory computer readable medium having instructions stored thereon that when executed by a processor cause the processor to perform a method of implementing a circuit design for an integrated circuit (IC), comprising:

placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths;

executing a timing analysis to determine a timing profile of the physical description, the timing profile including slack values for the plurality of paths based on a timing constraint;

optimizing the physical description by performing a plurality of iterations of;

selecting a candidate set of paths having negative slack from the plurality of paths in the physical description based on the slack values of the timing profile, the step of selecting including determining that timing of a particular path of the plurality of paths in the physical description having a most negative slack has not improved and excluding the particular path from the candidate set of paths; and

modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack;

generating a physical implementation of the circuit design for the IC based on the physical description.

16. The non-transitory computer readable medium of claim 15, further comprising:

excluding at least one additional path in a same clock group as the particular path from the candidate set of paths.

17. The non-transitory computer readable medium of claim 15, wherein the step of selecting comprises:

determining that timing improvement of a particular path of the plurality of paths in the physical description does not satisfy a threshold; and

excluding the particular path from the candidate set of paths.