Determination of word line to local source line shorts

• US 9,484,086 B2
• Filed: 07/10/2014
• Issued: 11/01/2016
• Est. Priority Date: 07/10/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Magia, Sagar, Sabde, Jagdish M.
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US14/328,027
• Publication Number:
  US 20160012914A1
• Time in Patent Office: 845 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/06 Acceleration testing

Abstract

A number of techniques determine defects in non-volatile memory arrays, which are particularly applicable to 3D NAND memory, such as BiCS type. Word line to word line shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used to determine word line to word line leaks between different blocks. Select gate leak line leakage, for both the word lines and other select lines, is considered, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques determine shorts between bit lines and low voltage circuitry, such as in sense amplifiers.

Claims

1. A method of determining whether one or more blocks of a semiconductor memory device are defective, the semiconductor memory device comprising a plurality of blocks, each block formed of a plurality of NAND strings having multiple memory cells connected in series between a source select gate and a drain select gate, the memory cells being respectively connected along word lines and the one or more source and drain select gates being respectively connected along a source select line and a drain select line, where each block is connected through a corresponding source select gate to a local source line, the method comprising:

performing a stress operation on a selected block of the plurality of blocks, comprising;

applying a high voltage to the local source line; and

concurrently setting the word lines, source select line, and drain select line to a low voltage;

subsequent to the stress operation, performing a defect determination operation, including;

performing a write operation on the selected block; and

determining whether the write operation was successful;

wherein the semiconductor memory device is a monolithic three-dimensional semiconductor memory device where the multiple memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium; and

wherein the NAND strings and the local source line run in a vertical direction relative to the substrate, and the word lines and the source select and drain select lines run in a horizontal direction relative to the substrate.

2. The method of claim 1, wherein determining whether the write operation was successful comprises determining that the number of memory cells connected along one word line that fail to verify exceeds a predetermined limit.

3. The method of claim 1, wherein determining whether the write operation was successful comprises determining that the write operation failed based on the number of programming loops exceeding a limit.

4. The method of claim 1, further comprising:

in response to determining that the write operation on the selected block was not successful, marking the selected block as defective.

5. The method of claim 1, wherein the determining whether the write operation was successful comprises:

subsequent to the write operation, performing a read operation on the selected block; and

determining whether data read from the selected block is corrupted.

6. The method of claim 5, wherein determining whether the data read from the selected block is corrupted includes comparing the data read from the selected block with data programmed into the selected block.

7. The method of claim 6, wherein the data as programmed is a predetermined pattern of known random data.

8. The method of claim 6, wherein determining whether the data read from the selected block is corrupted includes determining that the number of incorrect bits in the data as read exceeds a predetermined limit.

9. The method of claim 5, wherein determining whether the data read from the selected block is corrupted is based on an error correction code (ECC) result.

10. The method of claim 5, further comprising:

in response to determining that the data read from the selected block is corrupted, marking the block as defective.

11. The method of claim 1, wherein the defect determination operation further includes:

subsequent to the write operation, performing an erase on the selected block; and

determining whether the selected block is successfully erased.

12. The method of claim 11, further comprising:

in response to determining that the selected block is not successfully erased, marking the block as defective.

13. The method of claim 1, wherein the local source line of each block is connected to a global source line running in a horizontal direction relative to the substrate.

14. The method of claim 1, wherein the stress operation and subsequent defect determination operations are performed as a built-in self-test process.

15. The method of claim 1, wherein the stress operation and subsequent defect determination operations are performed after the semiconductor memory device has been operated over a plurality of erase cycles.

16. The method of claim 1, wherein the high voltage is within a range of programming voltages used during the write operation.

17. The method of claim 1, wherein the low voltage is a ground voltage.

18. The method of claim 1, wherein the low voltage is sufficient to turn on select transistors of the NAND strings.

19. The method of claim 1, wherein the low voltage is sufficient to turn on the multiple memory cells of the NAND strings.