Electronic storage device

• US 9,484,103 B1
• Filed: 07/20/2015
• Issued: 11/01/2016
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Lanuza, Reyjan C., Lukban, Jose Miguel N., Chong, Ryan C., Arcedera, Mark Ian A., Bruce, Rolando H.
• Primary Examiner(s): Elmore, Stephen
• Application Number:
  US14/803,107
• Time in Patent Office: 470 Days
• Field of Search: 711/202, 711/103, 711/156, 711/158, 711/165, 711/170, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Claims

1. A method comprising:

mapping a primary address to a set of minimum erasable locations in a storage device;

initializing the set;

obtaining and storing initialization parameters; and

initializing a section selection sequence that determines a first minimum writeable location in the set.

2. The method of claim 1, wherein the set of minimum erasable locations comprises a flash block in a non-volatile memory device.

3. The method of claim 1, wherein the set of minimum erasable locations comprises a plurality of flash blocks in a non-volatile memory device.

4. The method of claim 1, wherein initializing the set comprises erasing the set.

5. The method of claim 1, wherein the first minimum writable location comprises a flash section.

6. The method of claim 1, wherein the initialization parameters comprises at least one of the following:

a size of a minimum erasable location;

a size of a minimum writeable location;

a number of minimum erasable locations mapped to the primary address;

a sequence range; and

an invalid flash section location.

7. The method of claim 6, wherein the size of the minimum writable location comprises a flash block page.

8. The method of claim 1, wherein the section selection sequence indicates an available minimum writable location that can receive a write operation to store data associated with the primary address that is mapped to the set.

9. The method of claim 8, wherein the available minimum writable location is no longer in an erased state after a write operation is performed on the available minimum writable location and wherein the section selection sequence indicates another available minimum writable location that can receive a second write operation to store data associated with the primary address that is mapped to the set.

10. An apparatus comprising:

a storage device configured to map a primary address to a set of minimum erasable locations in a storage device, initialize the set, obtain and store initialization parameters, and initialize a section selection sequence that determines a first minimum writeable location in the set.

11. The apparatus of claim 10, wherein the set of minimum erasable locations comprises a flash block in a non-volatile memory device.

12. The apparatus of claim 10, wherein the set of minimum erasable locations comprises a plurality of flash blocks in a non-volatile memory device.

13. The apparatus of claim 10, wherein the storage device is configured to initialize the set by erasing the set.

14. The apparatus of claim 10, wherein the first minimum writable location comprises a flash section.

15. The apparatus of claim 10, wherein the initialization parameters comprises at least one of the following:

a size of a minimum erasable location;

a size of a minimum writeable location;

a number of minimum erasable locations mapped to the primary address;

a sequence range; and

an invalid flash section location.

16. The apparatus of claim 15, wherein the size of the minimum writable location comprises a flash block page.

17. The apparatus of claim 10, wherein the section selection sequence indicates an available minimum writable location that can receive a write operation to store data associated with the primary address that is mapped to the set.

18. The apparatus of claim 17, wherein the available minimum writable location is no longer in an erased state after a write operation is performed on the available minimum writable location and wherein the section selection sequence indicates another available minimum writable location that can receive a second write operation to store data associated with the primary address that is mapped to the set.

19. An article of manufacture, comprising:

a non-transient computer-readable medium having stored thereon instructions operable to permit an apparatus to;

map a primary address to a set of minimum erasable locations in a storage device;

initialize the set;

obtain and store initialization parameters; and

initialize a section selection sequence that determines a first minimum writeable location in the set.