Power savings via selection of SRAM power source

• US 9,484,115 B1
• Filed: 05/13/2015
• Issued: 11/01/2016
• Est. Priority Date: 05/13/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Golbus, Jason, Natarajan, Karthik, Jiang, Zhenye, Ren, Beibei, Voelkel, Eric, Felix, Stephen, Lin, Hwong-Kwo, Gold, Spencer, Guo, Jing, Gotterba, Andreas, Yang, Jun, Yang, Ge, Wang, Lei, Li, Yong, Chen, Hua, Gong, Haiyan
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US14/711,712
• Publication Number:
  US 20160336054A1
• Time in Patent Office: 538 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Claims

1. A computer-implemented method for supplying power to a memory module, the method comprising:

determining that a first circuit element within the memory module operates at a first voltage level;

determining that a second circuit element within the memory module operates at a nominal voltage level;

determining that the first voltage level exceeds the nominal voltage level by a first margin, wherein the first margin reflects an upper bound to noise associated with the nominal voltage level; and

causing the second circuit element to operate at the first voltage level.

2. The computer-implemented method of claim 1, further comprising:

determining that the first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determining that the second voltage level is less than the sum of the nominal voltage level and the first margin and greater than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level;

determining that performance is prioritized over power savings relative to the second circuit element; and

causing the second circuit element to operate at the second voltage level.

3. The computer-implemented method of claim 1, further comprising:

determining that the first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determining that the second voltage level is less than the sum of the nominal voltage level and the first margin and greater than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level;

determining that power savings is prioritized over performance relative to the second circuit element; and

causing the second circuit element to operate with the nominal voltage level.

4. The computer-implemented method of claim 1, further comprising:

determining that the first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determining that the second voltage level is less than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level; and

causing the second circuit element to operate at the nominal voltage level.

5. The computer-implemented method of claim 1, further comprising:

determining that the first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determining that the second voltage level is zero; and

causing the second circuit element to operate at the nominal voltage level.

6. The computer-implemented method of claim 1, wherein the first circuit element comprises logic that is configured to access the second circuit element.

7. The computer-implemented method of claim 1, wherein the second circuit element comprises a static random access memory array.

8. The computer-implemented method of claim 7, wherein the nominal voltage level comprises a minimum voltage level needed to support data retention within the static random access memory array.

9. A subsystem configured to supply power to a memory module, comprising:

a first circuit element within the memory module that operates at a first voltage level;

a second circuit element within the memory module that operates at a nominal voltage level; and

a control circuit configured to;

determine that the first voltage level exceeds the nominal voltage level by a first margin, wherein the first margin reflects an upper bound to noise associated with the nominal voltage level, and

apply the first voltage level to the second circuit element.

10. The subsystem of claim 9, wherein the control element is further configured to:

determine that the first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is less than the sum of the nominal voltage level and the first margin and greater than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level;

determine that performance is prioritized over power savings relative to the second circuit element; and

apply the second voltage level to the second circuit element.

11. The subsystem of claim 9, wherein the control element is further configured to:

determine that the first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is less than the sum of the nominal voltage level and the first margin and greater than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level;

determine that power savings is prioritized over performance relative to the second circuit element; and

apply the nominal voltage level to the second circuit element.

12. The subsystem of claim 9, wherein the control element is further configured to:

determine that first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is less than difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level; and

apply the nominal voltage level to the second circuit element.

13. The subsystem of claim 9, wherein the control element is further configured to:

determine that first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is zero; and

apply the nominal voltage level to the second circuit element.

14. The subsystem of claim 9, wherein the first circuit element comprises logic that is configured to access the second circuit element.

15. The subsystem of claim 9, wherein the second circuit element comprises a static random access memory array.

16. The subsystem of claim 15, wherein the nominal voltage level comprises a minimum voltage level needed to support data retention within the static random access memory array.

17. A computing device configured to supply power to a memory module, comprising:

a first circuit element within the memory module that operates at a first voltage level;

a second circuit element within the memory module that operates at a nominal voltage level; and

a control circuit configured to;

determine that the first voltage level exceeds the nominal voltage level by a first margin, wherein the first margin reflects an upper bound to noise associated with the nominal voltage level, and

apply the first voltage level to the second circuit element.

18. The computing device of claim 17, wherein the control element is further configured to:

determine that first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is less than the sum of the nominal voltage level and the first margin and greater than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level;

determine that performance is prioritized over power savings relative to the second circuit element; and

apply the second voltage level to the second circuit element.

19. The computing device of claim 17, wherein the control element is further configured to:

determine that first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is less than the sum of the nominal voltage level and the first margin and greater than the difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level;

determine that power savings is prioritized over performance relative to the second circuit element; and

apply the nominal voltage level to the second circuit element.

20. The computing device of claim 17, wherein the control element is further configured to:

determine that first circuit element has begun to operate at a second voltage level instead of operating at the first voltage level;

determine that the second voltage level is less than difference of the nominal voltage level and a second margin, wherein the second margin reflects a lower bound to noise associated with the nominal voltage level; and

apply the nominal voltage level to the second circuit element.