Semiconductor device having non-magnetic single core inductor and method of producing the same

• US 9,484,297 B2
• Filed: 03/13/2015
• Issued: 11/01/2016
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kim, Woo Sik, Lee, Ki Young, Chae, Moosung M.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US14/656,770
• Publication Number:
  US 20160268195A1
• Time in Patent Office: 599 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 28/10 Inductors

Abstract

Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the dielectric layer and in strips in the trench; forming metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias; filling the first metal line trenches, first vias, and trench; forming another dielectric layer and a second metal-oxide hard mask over the filled trench; forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias; and filling the second metal line trenches, second vias, and second trench.

Claims

1. A method comprising:

forming an inductor trench in a first dielectric layer;

forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the first dielectric layer and in strips in the inductor trench;

forming first metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias through both the first metal-oxide hard mask and the first dielectric layer;

filling the first metal line trenches, first vias, and inductor trench and removing the first metal-oxide hard mask from the first dielectric layer;

forming a second dielectric layer and a second metal-oxide hard mask over the filled inductor trench, first vias and first metal line trenches and the first dielectric layer;

forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias through both the second metal-oxide hard mask and the second dielectric layer down to the first metal line trenches and first vias, respectively; and

filling the second metal line trenches, second vias, and second trench.

2. The method of claim 1, further comprising:

disposing the first dielectric layer over an interlayer dielectric (ILD), the ILD including a contact therethrough.

3. The method according to claim 2, further comprising:

disposing a diffusion barrier layer between the ILD and the dielectric layer.

4. The method according to claim 3, further comprising:

disposing a hard mask over the first dielectric prior to forming the inductor trench.

5. The method of claim 1, wherein:

the metal in the metal-oxide hard mask forms the inductor bottom metal,

the filling of the inductor trench includes filling the inductor trench with an inductor core metal, and

the filling of the second trench includes filling the second trench with an inductor top metal.

6. The method according to claim 1, wherein the conformal oxide liner comprises tetraethyl orthosilicate (TEOS).

7. The method according to claim 1, comprising forming the inductor trench with a round or u-shaped bottom.

8. The method according to claim 1, comprising:

filling the first metal line trenches, first vias, and inductor trench by a damascene or dual damascene process.

9. The method according to claim 8, further comprising:

prior to filling the first metal line trenches, first vias, and inductor trench, depositing a barrier layer in the first metal line trenches, first vias, and inductor trench.

10. The method of claim 9, wherein the filling the first metal line trenches, first vias, and inductor trench comprises:

filling the first metal line trenches, first vias, and inductor trench with copper, tungsten or gold.

11. The method of claim 1, wherein the filling the second metal line trenches, second vias, and second trench, includes:

filling the second metal line trenches, second vias, and second trench with a conductive material selected from copper, tungsten or gold.

12. A method comprising:

disposing a dielectric layer over an interlayer dielectric (ILD), the ILD including a contact;

forming an inductor trench in the first dielectric layer;

forming a first metal-oxide hard mask over the first dielectric layer and in the inductor trench by disposing a metal hard mask followed by an oxide hard mask;

etching the metal-oxide hard mask in the inductor trench, forming strips;

forming first metal line trenches through the first metal-oxide hard mask on opposite sides of the inductor trench, while masking the inductor trench with a conformal oxide liner;

etching through the metal-oxide hard mask to extend some first metal line trenches into the first dielectric layer and other first metal line trenches through the first dielectric layer to form;

removing the first metal-oxide hard mask from the first dielectric layer;

filling the first metal line trenches, first vias, and inductor trench with a first metal;

forming a diffusion barrier, a second dielectric layer, and a second metal-oxide hard mask over the metal filled inductor trench, first vias, and first metal lines and the second dielectric layer;

forming a second trench through the second metal-oxide hard mask into the second dielectric layer;

etching through the second metal-oxide hard mask, second dielectric layer, and diffusion barrier to form second metal line trenches on opposite sides of the second trench and second vias down to the first metal line trenches and first vias, respectively, wherein a portion of the second dielectric layer and diffusion barrier remains over the inductor trench filled with the first metal; and

filling the second metal line trenches, second vias, and second trench with a second metal.

13. The method according to claim 12, further comprising:

prior to filling the first metal line trenches, first vias, and inductor trench with a first metal, depositing a barrier layer in the first metal line trenches, first vias, and inductor trench.

14. The method according to claim 12, comprising:

filling the first metal line trenches, first vias, and inductor trench with the first metal by a damascene or dual damascene process.