FinFET CMOS with Si NFET and SiGe PFET

• US 9,484,347 B1
• Filed: 12/15/2015
• Issued: 11/01/2016
• Est. Priority Date: 12/15/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Divakaruni, Ramachandra, Kim, Jeehwan
• Primary Examiner(s): Reames, Matthew
• Application Number:
  US14/969,833
• Time in Patent Office: 322 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.

Claims

1. A method for forming a complementary metal oxide semiconductor (CMOS) device, comprising:

growing a SiGe layer on a Si layer;

etching fins through the SiGe layer and the Si layer down to a buried dielectric layer;

forming spacers on sidewalls of the fins;

filling between the fins with a dielectric material on top of the buried dielectric layer;

replacing the SiGe layer with a dielectric cap for an n-type device to form a Si fin;

converting the Si semiconductor layer to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge;

recessing the dielectric material to below the spacers; and

removing the dielectric cap and the spacers to expose the Si fin and the SiGe fin.

2. The method as recited in claim 1, wherein growing the SiGe layer on the Si layer includes epitaxially growing the SiGe layer on the Si layer as a blanket layer.

3. The method as recited in claim 1, wherein etching fins includes patterning longitudinal fins through the SiGe layer and the Si layer.

4. The method as recited in claim 1, wherein etching fins includes patterning columnar fins through the SiGe layer and the Si layer.

5. The method as recited in claim 1, further comprising annealing the Si fin and the SiGe fin to round off corners of the Si fin and the SiGe fin.

6. The method as recited in claim 1, wherein the Si fin and the SiGe fin form nanowires.

7. The method as recited in claim 6, wherein the nanowires include one of longitudinal or vertical nanowires.

8. The method as recited in claim 1, wherein converting the Si layer to the SiGe fin includes exposing the SiGe layer to oxygen, water vapor or oxygen plasma at a temperature of between about 400 degrees C. to about 1050 degrees C. for one or more cycles.

9. A method for forming a complementary metal oxide semiconductor (CMOS) device, comprising:

growing a SiGe layer on a Si layer as a blanket layer;

etching fins through the SiGe layer and the Si layer down to a buried dielectric layer;

forming spacers on sidewalls of the fins;

filling between the fins with a dielectric material on top of the buried dielectric layer;

replacing the SiGe layer with a dielectric cap for an n-type device to form a Si fin;

converting the Si layer to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge;

recessing the dielectric material to below the spacers;

removing the dielectric cap and the spacers to expose the Si fin and the SiGe fin and to form a pedestal in the buried dielectric layer upon which each Si fin and SiGe fin rests;

forming a gate structure transversely to the S fins and the SiGe fin; and

epitaxially growing source and drain regions on the Si fin and the SiGe fin to form a CMOS device.

10. The method as recited in claim 9, wherein etching fins includes patterning longitudinal fins through the SiGe layer and the Si layer.

11. The method as recited in claim 9, wherein etching fins includes patterning columnar fins through the SiGe layer and the Si layer.

12. The method as recited in claim 9, further comprising annealing the Si fin and the SiGe fin to round off corners of the Si fin and the SiGe fin.

13. The method as recited in claim 9, wherein the Si fin and the SiGe fin form nanowires.

14. The method as recited in claim 9, wherein converting the Si layer to the SiGe fin includes exposing the SiGe layer to oxygen, water vapor or oxygen plasma at a temperature of between about 400 degrees C. to about 1050 degrees C. for one or more cycles.