Semiconductor device having an inter-layer via (ILV), and method of making same

• US 9,484,350 B2
• Filed: 09/27/2013
• Issued: 11/01/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Tsung-Hsien, Cheng, Hong-Chen, Lee, Cheng-Hung, Liao, Hung-Jen
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US14/039,481
• Publication Number:
  US 20150091098A1
• Time in Patent Office: 1,131 Days
• Field of Search: 257/401, 257/E27.026
• US Class Current: 1/1
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device.

Claims

1. A three dimensional semiconductor device comprising:

a first memory device;

a bit line connected to the first memory device;

a first drain via connected to the bit line and the first memory device;

a second memory device; and

a first via, wherein the first via connects a first source via of the first memory device to a second source via of the second memory device.

2. The semiconductor device of claim 1, further comprising an inter-layer dielectric (ILD), wherein the first memory device and the second memory device are separated by the ILD.

3. The semiconductor device of claim 2, wherein the first memory device, the second memory device and the ILD are in a stacked configuration, wherein the first memory device partially overlaps the second memory device.

4. The semiconductor device of claim 2, wherein a height of the ILD ranges from about 30 nm to about 140 nm.

5. The semiconductor device of claim 1, wherein the first memory device is electrically connected to the second memory device through the first via.

6. The semiconductor device of claim 1, further comprising:

a first word line; and

a second word line, wherein the first word line is connected to the first memory device and the second word line is connected to the second memory device.

7. The semiconductor device of claim 6, wherein the first memory device comprises:

a transistor device, wherein the first word line is configured to receive a first control signal, wherein the first control signal selectively switches on the transistor device.

8. The semiconductor device of claim 6, wherein the second memory device comprises:

a transistor device, wherein the second word line is configured to receive a first control signal, wherein the first control signal selectively switches on the transistor device.

9. The semiconductor device of claim 6, wherein the first memory device comprises a first transistor device;

and the second memory device comprises a second transistor device, wherein;

the first word line is configured to receive a first control signal;

the second word line is configured to receive a second control signal;

the first control signal selectively switches on the first transistor device; and

the second control signal selectively switches on the second transistor device.

10. The semiconductor device of claim 1, wherein the first via is an inter-layer via (ILV).

11. The semiconductor device of claim 1, wherein a height of the first via ranges from about 75 nanometers (nm) to about 140 nm.

12. The semiconductor device of claim 1, further comprising:

a second drain via connected to the second memory device and a ground terminal.

13. The semiconductor device of claim 1, further comprising:

a second via;

a first word line; and

a second word line electrically connected to the first word line by the second via.

14. A stacked semiconductor structure comprising:

a first memory device, the first memory device comprising;

a first transistor device;

a bit line, wherein the first transistor device is connected to the bit line by a first drain via;

a first word line, wherein the first transistor device is connected to the first word line;

a second memory device, the second memory device comprising;

a second transistor device;

an inter-layer dielectric (ILD), wherein the first memory device and the second memory device are separated by the ILD; and

a first via, wherein the first memory device is electrically connected to the second memory device by the first via.

15. The stacked semiconductor structure of claim 14, further comprising a second via, wherein:

the first memory device further comprises a first source via;

the second memory device further comprises;

a second source via; and

a second drain via;

the second drain via is electrically connected to a ground; and

the first source via is electrically connected to the second source via by the second via.

16. The stacked semiconductor structure of claim 14, wherein the first memory device further comprises a first source via, wherein the first source via is electrically connected to a ground.

17. The stacked semiconductor structure of claim 14, further comprising a second via, wherein:

the first memory device further comprises a first source via;

the second memory device further comprises;

a second source via; and

a second drain via;

the first source via is electrically connected to a ground;

the second source via is electrically connected to the ground; and

the first drain via is electrically connected to the second drain via by the second via.

18. A three dimensional integrated circuit, comprising:

a first memory device, comprising;

a first transistor device;

a bit line connected to the first transistor device;

a first word line connected to the first transistor device; and

a first drain via connected to the bit line and the first transistor device;

a second memory device, comprising;

a second transistor device; and

a second word line connected to the second transistor device; and

a first via connected to the first word line and the second word line,

wherein the first memory device partially overlaps the second memory device.

19. The three dimensional integrated circuit of claim 18, further comprising:

a second drain via connected to the second transistor device.

20. The three dimensional integrated circuit of claim 19, further comprising:

a first source via connected to the first transistor device and a ground;

a second source via connected to the second transistor device and the ground; and

a second via connected to the first drain via and the second drain via.