Method for forming a split-gate flash memory cell device with a low power logic device

• US 9,484,352 B2
• Filed: 12/17/2014
• Issued: 11/01/2016
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Wu, Chang-Ming, Liu, Shih-Chang
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US14/573,208
• Publication Number:
  US 20160181266A1
• Time in Patent Office: 685 Days
• Field of Search: 257315-316, 438/591
• US Class Current: 1/1
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor

Abstract

An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Claims

1. An embedded flash memory device comprising:

a gate stack including a control gate arranged over a floating gate;

an erase gate arranged adjacent to a first side of the gate stack;

a word line arranged adjacent to a second side of the gate stack that is opposite the first side, wherein the word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack;

a polysilicon logic gate with a top surface approximately even with the word line ledge;

an interlayer dielectric (ILD) layer arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word line; and

a contact extending through the ILD layer to one of the erase gate, the word line, and the polysilicon logic gate.

2. The embedded flash memory device according to claim 1, wherein the gate stack further includes a hard mask arranged over the control gate.

3. The embedded flash memory device according to claim 1, wherein the floating gate has a floating gate ledge exhibiting a reduced height relative to a top surface of the floating gate and surrounding a core region of the floating gate, and wherein the embedded flash memory device further includes:

a dielectric liner extending from the floating gate ledge over a top surface of the gate stack.

4. The embedded flash memory device according to claim 3, wherein the dielectric liner is an oxide-nitride-oxide (ONO) film.

5. The embedded flash memory device according to claim 1, wherein the top surface of the word line has a height of approximately 800 Angstroms, and wherein the word line ledge has a height of approximately 700 Angstroms.

6. The embedded flash memory device according to claim 1, further including:

silicide pads arranged over the word line, the erase gate, and the polysilicon logic gate.

7. The embedded flash memory device according to claim 1, wherein the top surface of the word line exhibits a reduced height relative to a top surface of the gate stack.

8. The embedded flash memory device according to claim 1, further including:

a second gate stack arranged on an opposite side of the erase gate as the gate stack, wherein the second gate stack includes a second control gate arranged over a second floating gate; and

a second word line arranged adjacent to the second gate stack on an opposite side of the second gate stack as the erase gate, wherein the second word line includes a second word line ledge exhibiting a reduced height relative to a top surface of the second word line;

wherein the top surface of the polysilicon logic gate is approximately even with the second word line ledge.

9. The embedded flash memory device according to claim 1, wherein the erase gate, the word line, and the polysilicon logic gate share a crystalline structure.

10. The embedded flash memory device according to claim 1, wherein an isolation region is arranged laterally between the gate stack and the polysilicon logic gate.

11. The embedded flash memory device according to claim 1, wherein a silicide pad extends to the top surface of the word line from the word line ledge, and further extends laterally across the top surface of the word line.

12. An integrated circuit for an embedded flash memory device, the integrated circuit comprising:

a pair of gate stacks laterally spaced over a semiconductor substrate, wherein each of the gate stacks comprises a floating gate and a control gate arranged over the floating gate;

an erase gate arranged between opposing bottommost sidewalls of the gate stacks;

a pair of word lines arranged on opposite outer sidewalls of the gate stacks, wherein the word lines include word line ledges exhibiting reduced heights relative to top surfaces of the word lines; and

a polysilicon logic gate with a top surface approximately even with the word line ledges.

13. The integrated circuit according to claim 12, wherein each of the gate stacks further comprises a hard mask arranged over the control gate.

14. The integrated circuit according to claim 12, wherein the floating gate has a floating gate ledge that exhibits a reduced height relative to a top surface of the floating gate and that surrounds a core region of the floating gate, and wherein the integrated circuit further comprises:

a dielectric liner extending over a top surface of one of the gate stacks from the floating gate ledge.

15. The integrated circuit according to claim 12, further comprising:

silicide pads arranged over the word lines, the erase gate, and the polysilicon logic gate.

16. The integrated circuit according to claim 12, wherein the top surfaces of the word lines exhibit reduced heights relative to top surfaces of the gate stacks.

17. The integrated circuit according to claim 12, wherein the erase gate, the word lines, and the polysilicon logic gate share a crystalline structure.

18. The integrated circuit according to claim 12, wherein an isolation region extends into the semiconductor substrate and is arranged laterally between one of the gate stacks and the polysilicon logic gate.

19. An integrated circuit comprising:

a memory cell comprising a gate stack arranged laterally between an erase gate and a word line, wherein the gate stack comprises a control gate arranged over a floating gate and a hard mask arranged over the control gate, and wherein the word line includes a ledge that is below a top surface of the word line;

a logic device laterally spaced from the memory cell and comprising a gate electrode, wherein a top surface of the gate electrode is even with the ledge, and wherein the gate electrode and the word line have a same crystalline structure; and

an interlayer dielectric (ILD) layer covering the memory cell and the logic device.

20. The integrated circuit according to claim 19, wherein a distance between opposite sidewall surfaces of the word line, at a location above the top surface of the gate electrode, is a same as a height of the gate electrode, and wherein one of the opposite sidewall surfaces faces the gate stack.