Methods of forming doped transition regions of transistor structures

• US 9,484,417 B1
• Filed: 07/22/2015
• Issued: 11/01/2016
• Est. Priority Date: 07/22/2015
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wu, Xusheng, Eller, Manfred
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US14/805,907
• Time in Patent Office: 468 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

Methods of forming doped transition regions of transistor structures are provided herein. The methods include, for instance: providing a first semiconductor material including a dopant over a source/drain region of the transistor structure; providing a second semiconductor material including the dopant over the first semiconductor material, where the second semiconductor material is different from the first semiconductor material; and, where providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into a portion of a channel region of the transistor structure. The portion of the channel region into which the dopant from the first semiconductor material diffuses forms the doped transition region.

Claims

1. A method comprising:

forming a doped transition region between a source/drain region of a transistor structure and a channel region of the transistor structure, the forming comprising;

providing a first semiconductor material comprising a dopant over the source/drain region;

providing a second semiconductor material comprising the dopant over the first semiconductor material, the second semiconductor material being different from the first semiconductor material;

wherein providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into the doped transition region;

wherein providing the second semiconductor material further comprises controllably diffusing the dopant so that the doped transition region is formed at least partially beneath one or more sidewalls of a gate structure and wherein the doped transition region does not extend into the channel region disposed beneath the gate of the gate structure;

wherein the transistor structure is a first transistor structure, the dopant is a first dopant, the doped transition region is a first doped transition region, the source/drain region is a first source/drain region and the channel region is a first channel region, and the method further comprises forming a second doped transition region of a second transistor structure,

wherein forming the second doped transition region comprises;

providing a third semiconductor material comprising a second dopant over a second source/drain region of the second transistor structure;

providing a fourth semiconductor material comprising the second dopant over the third semiconductor material, the second semiconductor material being different from the third semiconductor material; and

wherein providing the fourth semiconductor material is performed at a temperature sufficient to diffuse the second dopant from the third semiconductor material through the second source/drain region into the second doped transition region, and wherein the temperature sufficient to diffuse the second dopant from the third semiconductor material is insufficient to further diffuse the first dopant of the first transistor structure.

2. The method of claim 1, wherein providing the first semiconductor material comprises epitaxially growing the first semiconductor material.

3. The method of claim 1, wherein providing the second semiconductor material comprises epitaxially growing the second semiconductor material.

4. The method of claim 1, wherein the first semiconductor material comprises silicon, the second semiconductor material comprises silicon-germanium, and the dopant comprises a p-type dopant.

5. The method of claim 4, wherein the p-type dopant is boron.

6. The method of claim 1, wherein the first semiconductor material comprises silicon, the second semiconductor material comprises silicon-carbon, and the dopant comprises an n-type dopant.

7. The method of claim 6, wherein the n-type dopant is phosphorous.

8. The method of claim 1, wherein the third semiconductor material comprises silicon, the fourth semiconductor material comprises silicon-carbon, and the second dopant comprises an n-type dopant.

9. The method of claim 8, wherein the first semiconductor material comprises silicon, the second semiconductor material comprises silicon-germanium, and the first dopant comprises a p-type dopant.

10. The method of claim 9, wherein the p-type dopant is boron and the n-type dopant is phosphorous, and wherein the providing the fourth semiconductor material comprises epitaxially growing the fourth semiconductor material at a temperature between about 500°

C. and 700°

C.

11. The method of claim 1, wherein the transistor structure is a first transistor structure, the dopant is a first dopant, the doped transition region is a first doped transition region, the source/drain region is a first source/drain region and the channel region is a first channel region, and the method further comprises forming a second doped transition region of a second transistor structure, wherein forming the second doped transition region comprises:

providing, prior to providing the first semiconductor material and second semiconductor material, a third semiconductor material comprising a second dopant over a second source/drain region of the second transistor structure; and

wherein the temperature of providing the second semiconductor material is further sufficient to diffuse the second dopant from the third semiconductor material through the second source/drain region into the second doped transition region.

12. The method of claim 11, wherein the third semiconductor material comprises silicon-carbon, and the second dopant comprises an n-type dopant.

13. The method of claim 12, wherein the first semiconductor material comprises silicon, the second semiconductor material comprises silicon-germanium, and the first dopant comprises a p-type dopant.

14. The method of claim 13, wherein the providing the second semiconductor material comprises epitaxially growing the second semiconductor material at a temperature between about 500°

C. and 700°

C.