Integrated circuit structure with substrate isolation and un-doped channel

• US 9,484,461 B2
• Filed: 09/29/2014
• Issued: 11/01/2016
• Est. Priority Date: 09/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Chen, Guan-Lin
• Primary Examiner(s): WHALEN, DANIEL B
• Application Number:
  US14/500,606
• Publication Number:
  US 20160093726A1
• Time in Patent Office: 764 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate; a gate stack formed over the fin structure; source/drain regions over the substrate and disposed on opposing sides of the gate stack; a channel region defined in the fin structure and underlying the gate stack, wherein the channel region is un-doped; and a buried isolation layer disposed vertically between the channel region and the substrate, wherein the buried isolation layer includes a compound semiconductor oxide.

Claims

1. A semiconductor device comprising:

a fin structure formed on a substrate;

a gate stack formed over the fin structure;

source/drain regions over the substrate and disposed on opposing sides of the gate stack;

a channel region defined in the fin structure and underlying the gate stack, wherein the channel region is un-doped;

a buried isolation layer disposed vertically between the channel region and the substrate, wherein the buried isolation layer includes a compound semiconductor oxide, and wherein the buried isolation layer has a first thickness within the channel region and extends to the source/drain regions with a second thickness less than the first thickness; and

a semiconductor material layer disposed on the buried isolation layer within the source/drain regions.

2. The semiconductor device of claim 1, wherein the buried isolation layer is configured to completely electrically isolate the channel region from the substrate.

3. The semiconductor device of claim 1, wherein the buried isolation layer includes a silicon germanium oxide.

4. The semiconductor device of claim 3, wherein

the substrate is a silicon substrate;

the semiconductor material layer includes silicon germanium; and

the channel region includes silicon.

5. The semiconductor device of claim 4, wherein the semiconductor material layer has a thickness ranging from about 3 nm to about 15 nm.

6. The semiconductor device of claim 5, wherein a difference between the first and second thicknesses is greater than the thickness of the semiconductor material layer.

7. The semiconductor device of claim 4, wherein the channel region vertically spans from the buried isolation layer to the gate stack with a height ranging between about 10 nm and about 40 nm.

8. The semiconductor device of claim 1, wherein the gate stack includes a high k dielectric material layer and a metal electrode.

9. A semiconductor device comprising:

a fin structure formed on a substrate;

a gate stack formed over the fin structure;

source/drain regions over the substrate and disposed on opposing sides of the gate stack;

a channel region defined in the fin structure and underlying the gate stack;

a buried isolation layer of a compound semiconductor oxide, disposed vertically between the channel region and the substrate, extending to the source/drain regions, wherein the buried isolation layer includes a first thickness within the channel region and a second thickness within the source/drain regions, the second thickness being less than the first thickness; and

a compound semiconductor layer vertically disposed between the source/drain regions and the buried isolation layer, wherein the buried isolation layer includes silicon germanium oxide and the compound semiconductor layer includes silicon germanium.

10. The semiconductor device of claim 9, wherein

the buried isolation layer is configured to completely electrically isolate the channel region from the substrate.

11. The semiconductor device of claim 10, wherein the substrate is a silicon substrate, and the channel region is an un-doped silicon channel region.

12. The semiconductor device of claim 9, wherein a difference between the first and second thicknesses is greater than a thickness of the compound semiconductor layer.

13. A semiconductor device comprising:

a fin structure formed on a substrate;

a gate stack formed over the fin structure;

source/drain regions over the substrate and disposed on opposing sides of the gate stack;

a channel region defined in the fin structure and underlying the gate stack;

a buried isolation layer, disposed vertically between the channel region and the substrate, extending to the source/drain regions; and

a semiconductor layer vertically disposed between the source/drain regions and the buried isolation layer, wherein the semiconductor layer includes a material different from that of the channel region, and wherein the buried isolation layer includes oxygen and the material contained in the semiconductor layer.

14. The semiconductor device of claim 13, wherein the substrate is a silicon substrate, the semiconductor layer includes silicon germanium;

the channel region is an un-doped silicon channel region; and

the buried isolation layer is silicon germanium oxide.

15. The semiconductor device of claim 14, wherein the semiconductor material layer has a thickness ranging from 3 nm to 15 nm.

16. The semiconductor device of claim 13, wherein the buried isolation layer has a first thickness within the channel region and a second thickness within the source/drain regions, and the second thickness is less than the first thickness.

17. The semiconductor device of claim 16, wherein a difference between the first and second thicknesses is greater than a thickness of the semiconductor layer.

18. The semiconductor device of claim 13, wherein the gate stack includes a high k dielectric material layer and a metal electrode.

19. The semiconductor device of claim 13, wherein the buried isolation layer is configured to completely electrically isolate the channel region from the substrate.

20. The semiconductor device of claim 13, wherein the semiconductor material layer includes a compound semiconductor.