Semiconductor device, electrical device system, and method of producing semiconductor device

• US 9,484,472 B2
• Filed: 02/12/2014
• Issued: 11/01/2016
• Est. Priority Date: 02/13/2013
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Kasai, Hiroki
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US14/178,370
• Publication Number:
  US 20140225209A1
• Time in Patent Office: 993 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14676 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/02005 for device characterised by at least one potential jump barrier or surface barrier

Abstract

A semiconductor device includes a first semiconductor layer having a first conductive type; a circuit layer including a second semiconductor layer; and a plurality of layered members. Each of the layered members includes an interlayer insulation film and a wiring layer formed on the interlayer insulation film. The second semiconductor layer includes a circuit element. The layered members form a multilayer wiring layer. The semiconductor device further includes a penetrating conductive member; a conductive portion; and a first conductive type region. The penetrating conductive member penetrates from the first semiconductor layer to the interlayer insulation film of the layered member at the highest position. The conductive portion includes an electrode formed in the wiring layer of the layered member at the highest position and connected to the penetrating conductive member. The first conductive type region has an impurity concentration greater than that of the first semiconductor layer.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer having a first conductive type;

a circuit layer including a second semiconductor layer, said circuit layer being formed on one main surface of the first semiconductor layer, said second semiconductor layer including a circuit element and having a second conductive type opposite to the first conductive type;

a multilayer wiring layer including a first layered member at an uppermost position and a second layered member at a lowermost position;

a penetrating conductive member;

a conductive portion; and

a first conductive type region formed on the one main surface of the first semiconductor layer and connected to the conductive portion,

wherein each of said first layered member and said second layered member includes an interlayer insulation film and a wiring layer formed on the interlayer insulation film,

said wiring layer of the first layered member includes a connecting point connected to a positive electrode of a voltage applying unit or a ground;

said interlayer insulation film of the second layered member is situated on the circuit layer,

said wiring layer of the second layered member is connected to the circuit element,

said penetrating conductive member is disposed to penetrate from the one main surface of the first semiconductor layer to the interlayer insulation film of the first layered member through the circuit layer and the multi layer wiring layer,

said conductive portion includes an electrode formed in the wiring layer of the first layered member and connected to the penetrating conductive member,

said conductive portion is configured to be electrically isolated from both the circuit element and the wiring layer of the first layered member, and

said first conductive type region has an impurity concentration greater than that of the first semiconductor layer.

9. An electrical device system comprising said semiconductor device according to claim 1.

2. A semiconductor device, comprising:

a first semiconductor layer having a first conductive type;

an insulation member layer formed on one main surface of the first semiconductor layer;

a second semiconductor layer formed in the insulation member layer and having a second conductive type opposite to the first conductive type;

a circuit element formed on the second semiconductor layer; and

a multilayer wiring layer including a first layered member at an uppermost position and a second layered member at a lowermost position;

a penetrating conductive member;

a conductive portion;

a first region formed on the one main surface of the first semiconductor layer and having the second conductive type; and

a second region formed on the one main surface of the first semiconductor layer and having the first conductive type,

wherein each of said first layered member and said second layered member includes an interlayer insulation film and a wiring layer formed on the interlayer insulation film,

said wiring layer of the first layered member includes a connecting point connected to a positive electrode of a voltage applying unit or a ground;

said interlayer insulation film of the second layered member is situated on the insulation member layer;

said wiring layer of the second layered member is connected to the circuit element through a through electrode penetrating through the insulation member layer,

said penetrating conductive member is disposed to penetrate from the one main surface of the first semiconductor layer to the interlayer insulation film of the first layered member through the insulation member layer and the multi layer wiring layer,

said conductive portion includes an electrode formed in the wiring layer of the first layered member and connected to the penetrating conductive member,

said conductive portion is configured to be electrically isolated from both the circuit element and the wiring layer of the first layered member,

said first region is connected to the multilayer wiring layer through the through electrode, and

said second region is connected to the conductive portion and has an impurity concentration greater than that of the first semiconductor layer.

3. The semiconductor device according to claim 2, further comprising a third region disposed to surround the circuit element, the first region, and the second region,

wherein said third region has the first conductive type, and

said third region is connected to the electrode through the through electrode and has an impurity concentration greater than that of the first semiconductor layer.

4. The semiconductor device according to claim 2, further comprising a backside electrode disposed on another main surface of the first semiconductor layer opposite to the one main surface thereof,

wherein said backside electrode is connected to the first semiconductor layer.

5. The semiconductor device according to claim 2, wherein said first region and said second region are arranged to be one unit region,

said first region is disposed at a plurality of locations in the one unit region,

said second region is disposed at one location or a plurality of locations per the first region at the plurality of locations, and

said one unit region is arranged at a plurality of locations in an array pattern.

6. The semiconductor device according to claim 2, wherein said first semiconductor layer has an N-type as the first conductive type, and

said second semiconductor layer has a P-type as the second conductive type.

7. The semiconductor device according to claim 2, wherein said first semiconductor layer and said first region are configured to function as a sensor for detecting an X-ray.

8. The semiconductor device according to claim 3, wherein said voltage applying unit is configured to apply a negative potential to the first region and a positive potential to the third region.

10. A method of producing a semiconductor device, comprising the steps of:

preparing a layered member including a first semiconductor layer having a first conductive type, an insulation member layer on one main surface of the first conductive layer, and a second semiconductor layer on the insulation member layer;

forming a circuit element on the second semiconductor layer;

forming a first region and a second region on the one main surface of the first semiconductor layer, said first region having a second conductive type opposite to the first conductive type, said second region having the first conductive type and an impurity concentration greater than that of the first semiconductor layer;

forming a first interlayer insulation film on the second semiconductor layer;

forming a plurality of first through electrodes in a plurality of first through holes formed in the insulation member layer and the first interlayer insulation film through a plasma etching process so that one of the first through electrodes is connected to the circuit element and the first region, and another of the first through electrodes is connected to the second region;

forming a plurality of first conductive portions on the first interlayer insulation film, one of said first conductive portions being connected to the circuit element and the first region through the one of the first through electrodes, another of said first conductive portions being connected to the second region through the another of the first through electrodes and electrically isolated from the one of the first conductive portions;

forming a plurality of second through electrodes in a plurality of second through holes formed in a second interlayer insulation film through a plasma etching process so that one of the second through electrodes is connected to the one of the first conductive portions connected to the circuit element and the first region, and another of the second through electrodes is connected to the another of the first conductive portions connected to the second region; and

forming a plurality of second conductive portions on the second interlayer insulation film, one of said second conductive portions including a connecting point connected to a voltage applying unit or a ground, one of said second conductive portions being connected to the circuit element and the first region through the one of the first conductive portions and one of the second through electrodes, another of said second conductive portions being connected to the second region through another of the second through electrodes and the another of the first conductive portions,

wherein said another of the first through electrodes, said another of the first conductive portions, said another of the second through electrodes and said another of the second conductive portions are electrically isolated from the circuit element, the one of the first through electrodes, the one of the first conductive portions, the one of the second through electrodes, and the one of the second conductive portions.

11. The method of producing the semiconductor device according to claim 10, further comprising the step of repeating the steps of forming the second through electrodes and the second conductive portions several times.