Hall effect device

• US 9,484,525 B2
• Filed: 05/15/2012
• Issued: 11/01/2016
• Est. Priority Date: 05/15/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ausserlechner, Udo
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): McAndrew, Christopher
• Application Number:
  US13/472,012
• Publication Number:
  US 20130307609A1
• Time in Patent Office: 1,631 Days
• Field of Search: 324/251
• US Class Current: 1/1
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: H03K 17/90 by the use, as active elements, of galvano-magnetic devices, e.g. Hall-effect devices H03K17/95, H03K17/97 take precedence
• CPC Class Codes: H10N 52/01 Manufacture or treatment
• CPC Class Codes: H10N 52/101 Semiconductor Hall-effect devices
• CPC Class Codes: H10N 52/80 Constructional details

Abstract

Embodiments of the present invention provide a Hall effect device that includes a Hall effect region of a first semiconductive type, at least three contacts and a lateral conductive structure. The Hall effect region is formed in or on top of a substrate, wherein the substrate includes an isolation arrangement to isolate the Hall effect region in a lateral direction and in a depth direction from the substrate or other electronic devices in the substrate. The at least three contacts are arranged at a top of the Hall effect region to supply the Hall effect device with electric energy and to provide a Hall effect signal indicative of the magnetic field, wherein the Hall effect signal is generated in a portion of the Hall effect region defined by the at least three contacts. The lateral conductive structure is located between the Hall effect region and the isolation arrangement.

Claims

1. A Hall effect device indicative of a magnetic field, wherein the Hall effect device comprises:

a Hall effect region of a first semiconductive type formed in or on top of a substrate, wherein the substrate comprises an isolation arrangement to isolate the Hall effect region in a lateral direction and in a depth direction from the substrate or other electronic devices in the substrate;

at least three contacts arranged at a top of the Hall effect region to supply the Hall effect device with electric energy and to provide a Hall effect signal indicative of the magnetic field, wherein the Hall effect signal is generated in a portion of the Hall effect region defined by the at least three contacts; and

a lateral conductive structure of the first semiconductive type located between the Hall effect region and the isolation arrangement, wherein a doping concentration of the lateral conductive structure is higher than a doping concentration of the Hall effect region, wherein the lateral conductive structure comprises a ring shape that laterally surrounds the Hall effect region, and wherein the lateral conductive region and the Hall effect region are in ohmic contact to shield the Hall effect region from the isolation arrangement.

2. The Hall effect device according to claim 1, wherein the Hall effect device comprises a buried layer of the first semiconductive type formed in the substrate at a bottom of the Hall effect region, wherein a doping concentration of the buried layer is higher than a doping concentration of the Hall effect region.

3. The Hall effect device according to claim 1, wherein the lateral conductive structure is formed in the Hall effect region from the top of the Hall effect region in the depth direction towards a bottom of the Hall effect region.

4. The Hall effect device according to claim 1, wherein an electric conductivity of the lateral conductive structure is at least by a factor of 10 higher than an electric conductivity of the Hall effect region.

5. The Hall effect device according to claim 1, wherein the Hall effect device comprises a top plate arranged adjacent to the top of the Hall effect region and a dielectric top plate isolation arranged between the top plate and the top of the Hall effect region to isolate the top plate from the Hall effect region.

6. The Hall effect device according to claim 5, wherein the top plate comprises poly-silicon or metal.

7. The Hall effect device according to claim 5, wherein the dielectric top plate isolation comprises field oxide.

8. The Hall effect device according to claim 5, wherein a product of a relative permittivity of the dielectric top plate isolation and a thickness of the dielectric top plate isolation is equal to or greater than 1 μ

m.

9. The Hall effect device according to claim 1, wherein the isolation arrangement comprises an isolation region and a dielectric layer arranged between the isolation region and the Hall effect region, wherein the isolation arrangement is adapted to provide in an operation mode a homogenous potential over the isolation region.

10. The Hall effect device according to claim 1, wherein the substrate is of a second semiconductive type, wherein the isolation arrangement is adapted to provide in an operation mode a reverse biased semiconductor junction between the Hall effect region and the substrate.

11. The Hall effect device according to claim 1, wherein the Hall effect region comprises a doping concentration of at least 10^15/cm³.