Modulation circuit and operating method thereof

• US 9,484,859 B2
• Filed: 10/22/2015
• Issued: 11/01/2016
• Est. Priority Date: 11/05/2014
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Huang, Yen Lin, Chang, Hsiang-Hui, Chen, Hsin-Hung
• Primary Examiner(s): Gannon, Levi
• Application Number:
  US14/919,847
• Publication Number:
  US 20160126892A1
• Time in Patent Office: 376 Days
• Field of Search: 327/147, 327/156, 331/23, 332/127, 332/128
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/0958 applying frequency modulation by varying the characteristics of the voltage controlled oscillator
• CPC Class Codes: H03C 3/20 the element being a voltage-dependent capacitor
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit.

Claims

1. A modulation circuit, comprising:

a phase locked loop (PLL) circuit, for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal, the PLL circuit comprises;

a phase frequency detector, for detecting a phase difference between the reference signal and a divided signal;

a charge pump coupled to the phase frequency detector;

a loop filter, coupled to the charge pump, for outputting a filtered signal in response to the phase difference;

an oscillating module, for generating the output oscillating signal in response to the filtered signal and the first control signal, comprising;

a digital controlled capacitor bank, wherein the first control signal controls the capacitance of the digital controlled capacitor bank to adjust a frequency of the output oscillating signal; and

voltage tuning capacitor bank, for performing phase-locking in response to the filtered signal; and

the frequency divider, coupled to the oscillating module and the phase frequency detector, for dividing the frequency of the output oscillating signal by the divider value to generate the divided signal;

a scalar circuit, coupled to the PLL circuit, for receiving modulating data and generating the first control signal in response to the modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form;

a sigma-delta modulator for receiving the same modulating data and generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit;

a phase quantizer, for quantizing the phase difference information between reference signal and divided signal to generate quantized phase difference information in digital format; and

a calibration circuit, coupled to the phase quantizer, for calibrating an estimated tuning gain of the oscillating module in response to the quantized phase difference information.

2. The modulation circuit according to claim 1, wherein the digital controlled capacitor bank comprises:

a plurality of frequency tuning cells that each of which comprises a capacitor and a switch;

wherein the first control signal indicates an estimated tuning gain of the oscillating module, and the estimated tuning gain represents an estimated amount of frequency deviation that results from a unit-cell-change in the digital controlled capacitor bank.

3. The modulation circuit according to claim 1, wherein the calibration circuit comprises:

an accumulator, coupled to the phase quantizer, for accumulating the quantized phase difference information during a first time interval to obtain a first accumulated result and accumulating the quantized phase difference information during a second time interval to obtain a second accumulated result;

a first register, for storing the first accumulated result;

a second register, for storing the second accumulated result;

a comparator, coupled to the first register and the second register, for comparing the magnitude of the first accumulated result with the magnitude of the second accumulated result to generate a comparison result;

a gain compensator, coupled to the scalar circuit, for modifying the modulating data with a calibration gain; and

a gain searching circuit, coupled to the comparator and the gain compensator, for adjusting the calibration gain in response to the comparison result.

4. The modulation circuit according to claim 3, wherein the gain searching circuit comprises:

a sign bit register, for storing a sign bit of the comparison result; and

a successive approximation register (SAR), for adjusting the calibration gain according to the sign bit.

5. The modulation circuit according to claim 3, wherein the first time interval is a period of time that the PLL circuit is setting when a frequency step is applied to the PLL circuit via the first input and the second input, and the second time interval is another period of time that the PLL circuit is settled before the frequency step is applied to the PLL circuit.

6. The modulation circuit according to claim 3, wherein the first time interval is a period of time that the PLL circuit is setting when a frequency step is applied to the PLL circuit via the first input and the second input, and the second time interval is another period of time that the PLL circuit is settled when the frequency step is applied to the PLL circuit.

7. The modulation circuit according to claim 3, wherein lengths of the first time interval and the second time interval are equal.

8. The modulation circuit according to claim 1, wherein the calibration circuit comprises:

an accumulator, coupled to the detector, for accumulating the quantized phase difference information during the first time interval to generate the first accumulated result, and accumulating the quantized phase difference information during the second time interval to generate the second accumulated result;

a first register, for storing the first accumulated result;

a second register, for storing the second accumulated result;

a comparator, coupled to the first register and the second register, for comparing a magnitude of the first accumulated result with a magnitude of the second accumulated result to generate a comparison result; and

a gain searching circuit, coupled to the comparator, for adjusting the modulating data in response to the comparison result.

9. The modulation circuit according to claim 8, wherein the gain searching circuit comprises:

a sign bit register, for storing a sign bit of the comparison result of the first accumulated result and the second accumulated result; and

a SAR, for adjusting the modulating data according to the sign bit.

10. An operating method of a modulation circuit comprising a phase quantizer and a calibration circuit, comprising:

generating, by a phase locked loop (PLL) circuit, an output oscillating signal in response to a reference signal, a first control signal and a second control signal, wherein the PLL circuit comprises a phase frequency detector, a charge pump, a loop filter, an oscillating module and the frequency divider;

receiving modulating data and generating, by a scalar circuit coupled to the PLL circuit, the first control signal in response to the modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form;

receiving the same modulating data and generating, by a sigma-delta modulator coupled to the PLL circuit, the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit;

detecting, by the phase frequency detector, a phase difference between the reference signal and a divided signal;

outputting, by the loop filter, a filtered signal in response to the phase difference;

generating, by the oscillating module, the output oscillating signal in response to the filtered signal and the first control signal;

dividing, by the frequency divider, the frequency of the output oscillating signal by the divider value to generate the divided signal;

wherein the oscillating module comprises a digital controlled capacitor bank and a voltage tuning capacitor bank, the first control signal controls the capacitance of the digital controlled capacitor bank to adjust a frequency of the output oscillating signal, and the voltage tuning capacitor bank performs phase-locking in response to the filtered signal;

quantizing, by the phase quantizer, the phase difference information between reference signal and divided signal to generate quantized phase difference information in digital format; and

calibrating, by the calibration circuit, an estimated tuning gain of the oscillating module in response to the quantized phase difference information.

11. The operating method according to claim 10, wherein the digital controlled capacitor bank comprises:

a plurality of frequency tuning cells that each of which comprises a capacitor and a switch;

wherein the first control signal indicates an estimated tuning gain of the oscillating module, and the estimated tuning gain represents an estimated amount of frequency deviation that results from a unit-cell-change in the digital controlled capacitor bank.

12. The operating method according to claim 10, wherein the calibration circuit comprises an accumulator, a first register, a second register, a comparator, a gain compensator, and a gain searching circuit, and the operating method further comprises:

accumulating, by the accumulator, the quantized phase difference information during a first time interval to obtain a first accumulated result and accumulating the quantized phase difference information during a second time interval to obtain a second accumulated result;

storing, by the first register, the first accumulated result;

storing, by the second register, the second accumulated result;

comparing, by the comparator, the magnitude of the first accumulated result with the magnitude of the second accumulated result to generate a comparison result;

modifying, by the gain compensator, the modulating data with a calibration gain; and

adjusting, by the gain searching circuit, the calibration gain in response to the comparison result.

13. The operating method according to claim 12, wherein the gain searching circuit comprises a sign bit register and a successive approximation register (SAR), and the operating method further comprises:

storing, by the sign bit register, a sign bit of the comparison result; and

adjusting, by the SAR, the calibration gain according to the sign bit.

14. The operating method according to claim 12, wherein the first time interval is a period of time that the PLL circuit is setting when a frequency step is applied to the PLL circuit via the first input and the second input, and the second time interval is another period of time that the PLL circuit is settled before the frequency step is applied to the PLL circuit.

15. The operating method according to claim 12, wherein the first time interval is a period of time that the PLL circuit is setting when a frequency step is applied to the PLL circuit via the first input and the second input, and the second time interval is another period of time that the PLL circuit is settled when the frequency step is applied to the PLL circuit.

16. The operating method according to claim 12, wherein lengths of the first time interval and the second time interval are equal.

17. The operating method according to claim 10, wherein the calibration circuit comprises an accumulator, a first register, a second register, a comparator and a gain searching circuit, and the operating method further comprises:

accumulating, by the accumulator, the quantized phase difference information during the first time interval to generate the first accumulated result, and accumulating the quantized phase difference information during the second time interval to generate the second accumulated result;

storing, by the first register, the first accumulated result;

storing, by the second register, the second accumulated result;

comparing, by the comparator, a magnitude of the first accumulated result with a magnitude of the second accumulated result to generate a comparison result; and

adjusting, by the gain searching circuit, the modulating data in response to the comparison result.

18. The operating method according to claim 17, wherein the gain searching circuit comprises a sign bit register and a SAR, and the operating method further comprises:

storing, by the sign bit register, a sign bit of the comparison result of the first accumulated result and the second accumulated result; and

adjusting, by the SAR, the modulating data according to the sign bit.

19. An operating method of a modulation circuit, comprising:

generating, by a phase locked loop (PLL) circuit, an output oscillating signal in response to a reference signal, a first control signal and a second control signal;

receiving modulating data and generating, by a scalar circuit coupled to the PLL circuit, the first control signal in response to the modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form;

receiving the same modulating data and generating, by a sigma-delta modulator coupled to the PLL circuit, the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit;

applying a frequency step to the PLL circuit;

quantizing phase difference information indicating a phase difference between the reference signal and the divided signal;

accumulating the phase difference information during a first time interval and a second time interval to obtain a first accumulated result and a second accumulated result, respectively; and

calibrating an estimated tuning gain for an oscillating module of the PLL circuit according to a comparison result of the first accumulated result and the second accumulated result, wherein the oscillating module comprises a capacitor bank whose capacitance is adjusted in response to the frequency step.