Camera system encoder/decoder architecture

• US 9,485,419 B2
• Filed: 02/20/2016
• Issued: 11/01/2016
• Est. Priority Date: 10/01/2013
• Status: Expired due to Fees

• Current Assignee: GoPro, Inc.
• Original Assignee: GoPro, Inc.
• Inventors: Campbell, Scott Patrick, Mobbs, Paul, Adsumilli, Balineedu Chowdary, Chawla, Sumit
• Primary Examiner(s): LAM, HUNG H
• Application Number:
  US15/049,015
• Publication Number:
  US 20160173778A1
• Time in Patent Office: 255 Days
• Field of Search: 348/218.1, 348/222.1, 348/294, 348/333.02
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 3/4015 Image demosaicing, e.g. colour filter arrays [CFA] or Bayer patterns
• CPC Class Codes: H04N 1/6019 using look-up tables H04N1/6025 takes precedence
• CPC Class Codes: H04N 1/6027 Correction or control of colour gradation or colour contrast H04N1/6058 takes precedence
• CPC Class Codes: H04N 19/102 characterised by the element, parameter or selection affected or controlled by the adaptive coding
• CPC Class Codes: H04N 19/12 Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/156 Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
• CPC Class Codes: H04N 19/164 Feedback from the receiver or from the transmission channel
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/186 the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/1883 the unit relating to sub-band structure, e.g. hierarchical level, directional tree, e.g. low-high [LH], high-low [HL], high-high [HH]
• CPC Class Codes: H04N 19/33 in the spatial domain
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/517 by encoding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 23/13 with multiple sensors
• CPC Class Codes: H04N 23/60 : Control of cameras or camera modules
• CPC Class Codes: H04N 23/62 : Control of parameters via user interfaces
• CPC Class Codes: H04N 23/64 : Computer-aided capture of images, e.g. transfer from script file into camera, check of taken image quality, advice or proposal for image composition or decision on when to take image
• CPC Class Codes: H04N 23/667 : Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
• CPC Class Codes: H04N 23/6811 : based on the image signal
• CPC Class Codes: H04N 23/683 : performed by a processor, e.g. controlling the readout of an image memory
• CPC Class Codes: H04N 23/69 : Control of means for changing angle of the field of view, e.g. optical zoom objectives or electronic zooming
• CPC Class Codes: H04N 23/73 : by influencing the exposure time
• CPC Class Codes: H04N 23/80 : Camera processing pipelines; Components thereof
• CPC Class Codes: H04N 23/843 : Demosaicing, e.g. interpolating colour pixel values
• CPC Class Codes: H04N 23/88 : for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 23/90 : Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 9/8042 : involving data reduction

Abstract

An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Claims

1. A camera system, comprising:

an image sensor chip configured to produce image data representative of light incident upon the image sensor chip;

an image signal processor chip (“

ISP”

) configured to process the image data; and

an image capture accelerator chip (“

ICA”

) coupled between the image sensor chip and the ISP, the image capture accelerator comprising;

an input configured to receive the image data from the image sensor chip;

an encoder configured to, when the camera system is configured to operate in an accelerated capture mode, encode the received image data to produce encoded image data;

a memory configured to store the encoded image data;

a decoder configured to, when the camera system is configured to operate in a standby mode;

access the encoded image data from the memory; and

decode the encoded image data to produce decoded image data; and

an output configured to;

when the camera system is configured to operate in a normal capture mode, output the received image data to the ISP; and

when the camera system is configured to operate in the standby mode, output the decoded image data to the ISP.

2. The camera system of claim 1, wherein the encoder comprises a wavelet encoder, and wherein the decoder comprises a wavelet decoder.

3. The camera system of claim 1, wherein the encoded image data is not a displayable image format.

4. The camera system of claim 1, wherein the camera system is configured to operate in the accelerated captured mode in response to a rate of capturing image data by the image sensor chip exceeding a threshold.

5. The camera system of claim 1, wherein the ICA further comprises a memory controller coupled to the encoder, the decoder, and the memory.

6. The camera system of claim 5, wherein the memory includes a combination read/write communication bus coupled to the memory controller, the memory controller configured to write the encoded image data to the memory via the combination read/write communication bus in response to a request from the encoder, and configured to read the encoded image data from the memory via the combination read/write communication bus in response to a request from the decoder.

7. A method for capturing images by a camera system, comprising:

capturing, by an image sensor chip, light incident upon the image sensor to produce image data representative of the captured light;

when the camera system is configured to operate in a normal capture mode;

outputting the image data to an image signal processing chip (“

ISP”

);

when the camera system is configured to operate in an accelerated capture mode;

encoding, by an encoder of an image capture accelerator chip (“

ICA”

), the image data to produce encoded image data; and

storing, in a memory of the ICA, the encoded image data; and

when the camera system is configured to operate in a standby mode;

accessing the encoded image data from the memory;

decoding, by a decoder of the ICA, the encoded image data to produce decoded image data; and

outputting the decoded image data to the ISP.

8. The method of claim 7, wherein the encoder comprises a wavelet encoder, and wherein the decoder comprises a wavelet decoder.

9. The method of claim 7, wherein the encoded image data is not a displayable image format.

10. The method of claim 7, wherein the camera system is configured to operate in the accelerated captured mode in response to a rate of capturing image data by the image sensor chip exceeding a threshold.

11. The method of claim 7, wherein the ICA further comprises a memory controller coupled to the encoder, the decoder, and the memory.

12. The method of claim 11, wherein the memory includes a combination read/write communication bus coupled to the memory controller, the memory controller configured to write the encoded image data to the memory via the combination read/write communication bus in response to a request from the encoder, and configured to read the encoded image data from the memory via the combination read/write communication bus in response to a request from the decoder.

13. An image capture accelerator integrated circuit (“

ICA”

), comprising;

an input configured to receive image data captured by an image sensor chip;

an encoder configured to, when the ICA is configured to operate in an accelerated capture mode, encode the received image data to produce encoded image data;

a memory configured to store the encoded image data;

a decoder configured to, when the ICA is configured to operate in a standby mode;

access the encoded image data from the memory; and

decode the encoded image data to produce decoded image data; and

an output configured to;

when the ICA is configured to operate in a normal capture mode, output the received image data to an image signal processor chip (“

ISP”

); and

when the ICA is configured to operate in the standby mode, output the decoded image data to the ISP.

14. The ICA of claim 13, wherein the encoder comprises a wavelet encoder, and wherein the decoder comprises a wavelet decoder.

15. The ICA of claim 13, wherein the encoded image data is not a displayable image format.

16. The ICA of claim 13, wherein the ICA is configured to operate in the accelerated captured mode in response to a rate of capturing image data by the image sensor chip exceeding a threshold.

17. The ICA of claim 13, wherein the ICA further comprises a memory controller coupled to the encoder, the decoder, and the memory.

18. The ICA of claim 17, wherein the memory includes a combination read/write communication bus coupled to the memory controller, the memory controller configured to write the encoded image data to the memory via the combination read/write communication bus in response to a request from the encoder, and configured to read the encoded image data from the memory via the combination read/write communication bus in response to a request from the decoder.