Image capture accelerator

• US 9,485,422 B2
• Filed: 09/17/2014
• Issued: 11/01/2016
• Est. Priority Date: 10/01/2013
• Status: Expired due to Fees

• Current Assignee: GoPro, Inc.
• Original Assignee: GoPro, Inc.
• Inventors: Campbell, Scott Patrick, Mobbs, Paul, Adsumilli, Balineedu Chowdary, Chawla, Sumit
• Primary Examiner(s): LAM, HUNG H
• Application Number:
  US14/488,283
• Publication Number:
  US 20150092076A1
• Time in Patent Office: 776 Days
• Field of Search: 348/218.1, 348/222.1, 348/294, 348/333.02
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 3/4015 Image demosaicing, e.g. colour filter arrays [CFA] or Bayer patterns
• CPC Class Codes: H04N 1/6019 using look-up tables H04N1/6025 takes precedence
• CPC Class Codes: H04N 1/6027 Correction or control of colour gradation or colour contrast H04N1/6058 takes precedence
• CPC Class Codes: H04N 19/102 characterised by the element, parameter or selection affected or controlled by the adaptive coding
• CPC Class Codes: H04N 19/12 Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/156 Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
• CPC Class Codes: H04N 19/164 Feedback from the receiver or from the transmission channel
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/186 the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/1883 the unit relating to sub-band structure, e.g. hierarchical level, directional tree, e.g. low-high [LH], high-low [HL], high-high [HH]
• CPC Class Codes: H04N 19/33 in the spatial domain
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/517 by encoding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 23/13 with multiple sensors
• CPC Class Codes: H04N 23/60 : Control of cameras or camera modules
• CPC Class Codes: H04N 23/62 : Control of parameters via user interfaces
• CPC Class Codes: H04N 23/64 : Computer-aided capture of images, e.g. transfer from script file into camera, check of taken image quality, advice or proposal for image composition or decision on when to take image
• CPC Class Codes: H04N 23/667 : Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
• CPC Class Codes: H04N 23/6811 : based on the image signal
• CPC Class Codes: H04N 23/683 : performed by a processor, e.g. controlling the readout of an image memory
• CPC Class Codes: H04N 23/69 : Control of means for changing angle of the field of view, e.g. optical zoom objectives or electronic zooming
• CPC Class Codes: H04N 23/73 : by influencing the exposure time
• CPC Class Codes: H04N 23/80 : Camera processing pipelines; Components thereof
• CPC Class Codes: H04N 23/843 : Demosaicing, e.g. interpolating colour pixel values
• CPC Class Codes: H04N 23/88 : for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 23/90 : Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 9/8042 : involving data reduction

Abstract

An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Claims

1. A camera system, comprising:

an image sensor configured to produce image data representative of light incident upon the image sensor during a capture interval;

an image signal processor (“

ISP”

) with a first input and a second input; and

an image capture accelerator integrated circuit chip (“

ICA”

) coupled between the image sensor and the ISP, the ICA comprising;

an input configured to receive the image data from the image sensor;

a first output configured to output image data at a first resolution, the first output coupled to the first input of the ISP;

a compression engine configured to decimate the received image data into a plurality of image sub-band components; and

a second output configured to output to an image sub-band component, the second output coupled to the second input of the ISP, the image sub-band component comprising a second resolution lower than the first resolution.

2. The camera system of claim 1, wherein the ICA is configured to output the received image data via the first output.

3. The camera system of claim 1, wherein the outputted image sub-band component is a low/low sub-band component.

4. The camera system of claim 1, wherein the second resolution is one quarter the resolution of the first resolution.

5. The camera system of claim 1, wherein the received image data comprises raw Bayer image data.

6. The camera system of claim 5, wherein the ICA further comprises:

a transformation engine configured to convert the received raw Bayer image data into a red color component, a blue color component, a first green color component and a second green color component.

7. The camera system of claim 1, wherein the compression engine is further configured to perform entropy encoding on one or more of the plurality of image sub-band components.

8. The camera system of claim 1, wherein the ICA further comprises:

a demultiplexor configured to provide the received image data to the first input of the ISP in a first configuration, and configured to provide the received image data to the compression engine in a second configuration.

9. The camera system of claim 1, wherein the ISP is configured to encode image data received via the second input for display as a preview image.

10. The camera system of claim 1, wherein the ISP is configured to encode image data receive via the first input for storage in a memory coupled to the ISP.

11. A method for processing images captured by a camera system, comprising:

capturing, by an image sensor, light incident upon the image sensor to produce image data representative of the captured light;

receiving, by an image capture accelerator integrated circuit chip (“

ICA”

), the image data from the image sensor;

outputting, by the ICA, the image data to a first input of an image signal processor (“

ISP”

), the image data comprising a first resolution;

decimating, by the ICA, the received image into a plurality of image sub-band components; and

outputting, by the ICA, an image sub-band component to a second input of the ISP, the image sub-band component comprising a second resolution lower than the first resolution.

12. The method of claim 11, wherein the outputted image sub-band component is a low/low sub-band component.

13. The method of claim 11, wherein the second resolution is one quarter the resolution of the first resolution.

14. The method of claim 11, wherein the ISP is configured to encode image data received via the second input for display as a preview image.

15. The method of claim 11, wherein the ISP is configured to encode image data received via the first input for storage in a memory coupled to the ISP.

16. An accelerator circuit chip for a camera system, comprising:

an input configured to receive image data from an image sensor, the image data representative of light incident upon the image sensor during a capture interval;

a first output configured to output image data, the first output coupled to a first input of an image signal processor (“

ISP”

), the image data comprising a first resolution;

a compression engine configured to decimate the received image data into a plurality of image sub-band components; and

a second output configured to output to an image sub-band component, the second output coupled to a second input of the ISP, the image sub-band component comprising a second resolution lower than the first resolution.

17. The accelerator circuit chip of claim 16, wherein the outputted image sub-band component is a low/low sub-band component.

18. The accelerator circuit chip of claim 16, wherein the second resolution is one quarter the resolution of the first resolution.

19. The accelerator circuit chip of claim 16, wherein the ISP is configured to encode image data received via the second input for display as a preview image.

20. The accelerator circuit chip of claim 16, wherein the ISP is configured to encode image data received via the first input for storage in a memory coupled to the ISP.