Assembly bonding

• US 9,488,853 B2
• Filed: 04/03/2015
• Issued: 11/08/2016
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Verily Life Sciences LLC (Alphabet Inc.)
• Original Assignee: Verily Life Sciences LLC (Alphabet Inc.)
• Inventors: Etzkorn, James
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US14/678,198
• Publication Number:
  US 20150212340A1
• Time in Patent Office: 585 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: A61B 2562/12 Manufacturing methods specially adapted for producing sensors for in-vivo measurements
• CPC Class Codes: A61B 5/6821 Eye
• CPC Class Codes: B29D 11/00048 composed of parts with dissimilar composition B29D11/00057 takes precedence
• CPC Class Codes: B29D 11/00807 Producing lenses combined with electronics, e.g. chips
• CPC Class Codes: G02C 11/10 Electronic devices other than hearing aids
• CPC Class Codes: G02C 7/04 Contact lenses for the eyes disinfection or sterilisation of contact lenses A61L12/00
• CPC Class Codes: G02C 7/049 Contact lenses having special fitting or structural features achieved by special materials or material structures
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/11312 Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/291 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/8012 : Aligning
• CPC Class Codes: H01L 2224/8085 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/81903 : by means of a layer connector
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/9211 : Parallel connecting processes
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/742 : Apparatus for manufacturing bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/20105 : Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/20641 : larger or equal to 100 microns less than 200 microns
• CPC Class Codes: H01L 2924/20642 : larger or equal to 200 microns less than 300 microns
• CPC Class Codes: H01L 2924/20643 : larger or equal to 300 microns less than 400 microns
• CPC Class Codes: H01L 2924/20644 : larger or equal to 400 microns less than 500 microns
• CPC Class Codes: H01L 2924/20645 : larger or equal to 500 microns less than 600 microns
• CPC Class Codes: H01L 2924/20646 : larger or equal to 600 microns less than 700 microns
• CPC Class Codes: H01L 2924/20647 : larger or equal to 700 microns less than 800 microns
• CPC Class Codes: H01L 2924/20648 : larger or equal to 800 microns less than 900 microns
• CPC Class Codes: H01L 2924/20649 : larger or equal to 900 microns less than 1000 microns
• CPC Class Codes: H01L 2924/2065 : larger or equal to 1000 microns less than 1500 microns

Abstract

A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate.

Claims

1. A method for manufacturing a device having an integrated circuit, comprising:

creating a plurality of chip contact pads on a chip by forming a first grid of metal lines on a surface of the chip, wherein the chip contact pads correspond to intersection points of the metal lines in the first grid;

creating a plurality of substrate contact pads on a substrate by forming a second grid of metal lines on a surface of the substrate, wherein the substrate contact pads correspond to intersection points of the metal lines in the second grid and wherein the plurality of substrate contact pads correspond to the plurality of chip contact pads;

applying assembly bonding material to each of the plurality of substrate contact pads formed on the substrate; and

bonding the plurality of chip contact pads to the plurality of substrate contact pads via the assembly bonding material to bond the chip to the substrate.

2. The method of claim 1, wherein:

forming the first grid of metal lines comprises forming the first grid of metal lines using photolithography; and

forming the second grid of metal lines comprises forming the second grid of metal lines using photolithography.

3. The method of claim 1, further comprising sealing the chip on the substrate.

4. The method of claim 1, wherein the chip has a thickness of about 100 microns or less and a length of about 1.0 millimeter or less.

5. The method of claim 1, wherein the assembly bonding material includes an isotropic conductive material.

6. The method of claim 1, wherein the substrate comprises a polymer material.

7. The method of claim 1, wherein the bonding is performed employing a flip-chip bonder.

8. A device having an integrated circuit disposed thereon or therein formed by a process comprising:

creating a plurality of chip contact pads on a chip by forming a first grid of metal lines on a surface of the chip, wherein the chip contact pads correspond to intersection points of the metal lines in the first grid;

creating a plurality of substrate contact pads on a substrate by forming a second grid of metal lines on a surface of the substrate, wherein the substrate contact pads correspond to intersection points of the metal lines in the second grid and wherein the plurality of substrate contact pads correspond to the plurality of chip contact pads;

applying assembly bonding material to each of the plurality of chip contact pads; and

bonding the plurality of the chip contact pads to the plurality of substrate contact pads formed on the substrate via the assembly bonding material to bond the chip to the substrate.

9. The device of claim 8, wherein:

forming the first grid of metal lines comprises forming the first grid of metal lines using photolithography; and

forming the second grid of metal lines comprises forming the second grid of metal lines using photolithography.

10. The device of claim 8, wherein the process further comprises sealing the chip on the substrate.

11. The device of claim 8, wherein the chip has a thickness of about 100 microns or less and a length of about 1.0 millimeter or less.

12. The device of claim 8, wherein the bonding is performed employing a flip-chip bonder.

13. The device of claim 8, wherein the assembly bonding material includes an anisotropic conductive material.

14. The device of claim 8, wherein the substrate comprises a polymer material.

15. A method for manufacturing a device having an integrated circuit, comprising:

creating a plurality of substrate contact pads on a substrate, wherein the plurality of substrate contact pads correspond to intersection points of a grid of metal lines on a surface of the substrate;

creating a plurality of chip contact pads on a chip, wherein the plurality of chip contact pads correspond to intersection points of a grid of metal lines on the chip, and wherein the plurality of chip contact pads correspond to the plurality of substrate contact pads;

applying assembly bonding material to the each of the plurality of substrate contact pads or chip contact pads, wherein the assembly bonding material includes an anisotropic conductive material;

aligning the plurality of substrate contact pads with the plurality of chip contact pads; and

bonding the chip to the substrate via the assembly bonding material using flip chip bonding.

16. The method of claim 15, wherein creating the plurality of the substrate contact pads comprises forming the grid of metal lines on the substrate using photolithography.

17. The method of claim 15, wherein creating the plurality of the substrate contact pads comprises forming a plurality of metal squares at the intersections points of the grid of metal lines on the substrate, each of the plurality of metal squares having a length of about 100 microns or less.

18. The method of claim 15, wherein creating the plurality of the chip contact pads comprises forming the grid of metal lines on the chip using photolithography.

19. The method of claim 15, wherein forming the device further comprises sealing the chip on the substrate.

20. The method of claim 15, wherein the chip has a thickness of about 100 microns or less and a length of about 1.0 millimeter or less.