Folded memory modules

• US 9,489,323 B2
• Filed: 02/18/2014
• Issued: 11/08/2016
• Est. Priority Date: 02/20/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Amirkhany, Amir, Rajan, Suresh, Kollipara, Ravindranath, Shaeffer, Ian, Secker, David A.
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US14/182,986
• Publication Number:
  US 20140237152A1
• Time in Patent Office: 994 Days
• Field of Search: 710/305, 710/310, 710/316, 711/5, 711/154
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Claims

1. A memory system, comprising:

a motherboard comprising a plurality of motherboard data lines;

a first memory module coupled to at least a first subset of the plurality of motherboard data lines via the first memory module slot, the first memory module comprising a first memory core associated with a first rank and a second memory core associated with a second rank, the first memory module including a first data path to couple the first subset of the plurality of motherboard data lines to the first memory core and to the second memory core;

a second memory module coupled to at least a second subset of the plurality of motherboard data lines via the second memory module slot, the second memory module comprising a third memory core associated with the first rank and a fourth memory core associated with the second rank, the second memory module including a second data path to couple the second subset of the plurality of motherboard data lines to the third memory core and to the fourth memory core;

wherein the first memory core and the third memory core associated with the first rank are each accessible by a memory controller when a first select line associated with the first rank is enabled, and the first memory core and the third memory core associated with the first rank are each inaccessible to the memory controller when the first select line is disabled;

wherein the second memory core and the fourth memory core associated with the second rank are each accessible by a memory controller when a second select line associated with the second rank is enabled, and the second memory core and the fourth memory core associated with the second rank are each inaccessible to the memory controller when the second select line is disabled.

2. The memory system of claim 1, wherein the first memory module comprises:

a data interface including a plurality of data pins coupled to each of the plurality of data lines;

a plurality of configurable switches coupled between the data interface and the first data path, each of the configurable switches coupled between one of the plurality of data pins and a corresponding one of a plurality of memory module data lines and when enabled coupling said one of the plurality of data pins to said corresponding one of the plurality of memory module data lines, and when disabled decoupling said one of the plurality of data pins from said corresponding one of the plurality of memory module data lines.

3. The memory system of claim 2, wherein the plurality of memory module data lines includes first side memory module data lines coupled to the plurality of configurable switches and second side memory module data lines coupled to the first and second memory cores, the memory module further comprises:

a buffer to route the data between a first subset of the first side memory module data lines and a first subset of the second side memory module data lines during a first time when the first select line is enabled and the second select line is disabled, and to route the data between the first subset of the first side memory module data lines and a second subset of the second side memory module data lines during a second time when the first select line is disabled and the second select line is enabled.

4. The memory system of claim 3, wherein the buffer further comprises:

a mode register to store a mode register value, the mode register value being output to the plurality of configurable switches to enable a subset of the plurality of configurable switches.

5. The memory system of claim 2, further comprising:

a control pin to receive a control value from the memory controller, the control pin to output the control value to the plurality of configurable switches to enable a subset of the configurable switches.

6. The memory system of claim 2, further comprising:

a manual switch to control a control value output to the plurality of configurable switches to enable a subset of the plurality of configurable switches.

7. The memory system of claim 2, wherein each of the first and second memory cores comprises:

a mode register to store a mode register value, the mode register value being output to one or more of the plurality of configurable switches to enable said one or more of the plurality of configurable switches.

8. The memory system of claim 2, further comprising:

a first control line to collectively enable or disable each of a first subset of the plurality of configurable switches; and

a second control line to collectively enable or disable each of a second subset of the plurality of configurable switches.

9. The memory system of claim 8, wherein the first subset of the plurality of configurable switches and the second subset of the plurality of configurable switches each comprise half of the plurality of configurable switches.

10. The memory system of claim 1, wherein the first memory module further comprises:

a buffer to route the data between the first subset of the plurality of motherboard data lines and the first memory core during a first time and to route the data between the first subset of the plurality of motherboard data lines and the second memory core during a second time.

11. The memory system of claim 1, wherein the first memory module comprises:

a plurality of data pins;

memory logic to configure a width of the first memory module, the memory logic including a mode register to generate switch control signals to enable or disable a plurality of switches based on the configured width, the plurality of switches coupled between the plurality of data pins and the first memory core, the first memory core to store data read on the plurality of data pins in response to a write command and to output data to the plurality of data pins in response to a read command.

12. The memory of claim 11, wherein the mode register generates an odd enable signal and an even enable signal to configure the first memory module as one of an odd memory and an even memory, wherein the odd enable signal comprises a first logic value and the even enable signal comprises a second logic value when the first memory module is configured as an odd memory, and wherein the even enable signal comprises the first logic value and the odd enable signal comprises the second logic value when the first memory module is configured as an even memory.

13. The memory system of claim 1, further comprising a memory controller, the memory controller comprising:

a plurality of data pins to communicate data to and from the first memory module;

a command address pin to output a command address signal to control a read operation to read data on the plurality of data pins, and the command address signal to control a write operation to write data to the plurality of data pins; and

enable pins to output an enable signal to enable or disable one or more of a plurality of configurable switches on the first memory module; and

memory controller logic to generate the enable signal based on a configuration of the first memory module.

14. The memory controller of claim 13, wherein the enable pins comprise an odd enable pin and even enable pin, wherein the memory controller logic is further to provide a first logic value to the odd enable pin and a second logic value to the even enable pin to configure the first memory module as an odd memory module, and the memory controller logic to provide the second logic value to the even enable pin and the first logic value to the odd enable pin to configure the first memory module as an even memory module.

15. The memory system of claim 1, wherein the first memory module further comprises a buffer, the buffer, comprising:

a mode register to enable or disable one or more of a plurality of configurable switches;

memory controller side data lines coupled to the plurality of configurable switches, the memory controller side data lines including a first subset of the memory controller side data lines coupled to enabled switches of the plurality of configurable switches, and the memory controller side data lines including a second subset of the memory controller side data lines coupled to disabled switches of the plurality of configurable switches, the first subset of the memory controller side data lines configured to communicate data to and from the memory controller;

memory core side data lines to communicate the data to and from the first and second memory cores;

a data router coupled between the memory controller side data lines and the memory core side data lines, the data router to route the data between the first subset of the memory controller side data lines and a first subset of the memory core side data lines during a first time when the first select line is enabled and the second select line is disabled, and to route the data between the first subset of the memory controller side data lines and a second subset of the memory core side data lines during a second time when the first select line is disabled and the second select line is enabled.

16. The memory system of claim 1, wherein each of the plurality of data lines on the motherboard are coupled to each of the first and second memory module slots.

17. The memory system of claim 1, wherein only the first subset of the plurality of data lines on the motherboard are coupled to the first memory module slot and only the second subset of the plurality of data lines on the motherboard are coupled to the second memory module slot.