Reliability-optimized selective voltage binning

• US 9,489,482 B1
• Filed: 06/15/2015
• Issued: 11/08/2016
• Est. Priority Date: 06/15/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bickford, Jeanne P., Habib, Nazmul, Li, Baozhen, Wilder, Tad J.
• Primary Examiner(s): Nguyen, Nha
• Application Number:
  US14/739,436
• Time in Patent Office: 512 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed is a method for improving integrated circuit (IC) chip reliability. In the method, IC chips, which are manufactured according to a given IC chip design, are sorted into multiple different groups associated with different process windows in the process distribution for the design. Different operating voltages are assigned to the different groups, respectively, in order to optimize overall reliability of IC chips across the process distribution. That is, each group is associated with a specific process window, comprises a specific portion of the IC chips and is assigned a group-specific operating voltage that minimizes the fail rate of the specific portion of the IC chips and that, thereby optimizes the reliability of the specific portion of the IC chips. The group-specific operating voltage will be within minimum and maximum voltages associated with either the process distribution or the specific process window (e.g., following power-optimized selective voltage binning).

Claims

1. A method comprising:

sorting integrated circuit chips manufactured according to a design into groups, said groups being associated with different process windows of a process distribution for said design;

determining group-specific operating voltages to be assigned to said groups, said determining comprising, for each group;

identifying a specific selected voltage that achieves a lowest group fail rate; and

using said specific selected voltage as a group-specific operating voltage for said group; and

assigning said group-specific operating voltages to said groups to optimize overall reliability of said integrated circuit chips across said process distribution,

said reliability being based on said group fail rate, and

each group being associated with one of said process windows, comprising a specific portion of said integrated circuit chips and being assigned a group-specific operating voltage that optimizes reliability of said specific portion of said integrated circuit chips.

2. The method of claim 1, said group-specific operating voltages being within a minimum voltage and a maximum voltage associated with said process distribution.

3. The method of claim 1, said determining said group-specific operating voltages to be assigned to said groups further comprising, for each group:

determining a group fail rate as a function of a selected voltage; and

iteratively repeating said determining of said group fail rate using different selected voltages.

4. The method of claim 3,

said group fail rate being determined as a sum of chip fail rates of integrated circuit chips within said group divided by a number of said integrated circuit chips in said group, and

each chip fail rate being determined based on multiple failure mechanism fail rates.

5. The method of claim 1, said group-specific operating voltages varying between said groups.

6. The method of claim 1, further comprising:

programming each integrated circuit chip in said group with an identifier associated with said group; and

,

creating a look-up table that associates said identifier with said group-specific operating voltage.

7. The method of claim 1, further comprising programming each integrated circuit chip in said group with said group-specific operating voltage.

8. A method comprising:

sorting integrated circuit chips manufactured according to a design into groups, said groups being associated with different process windows of a process distribution for said design;

determining group-specific operating voltage ranges to be assigned to said groups, said determining comprising, for each group;

identifying a specific selected voltage range that achieves a lowest group fail rate; and

using said specific selected voltage range as a group-specific operating voltage range for said group;

measuring leakage power of said integrated circuit chips to produce leakage power measurements; and

assigning said group-specific operating voltage ranges to said groups to minimize power consumption of said integrated circuit chips across said process distribution, said power consumption being based on said leakage power measurements; and

assigning group-specific operating voltages to said groups to optimize overall reliability of said integrated circuit chips across said process distribution, said reliability being based on said group fail rate, and

each group being associated with one of said process windows, comprising a specific portion of said integrated circuit chips and being assigned a group-specific operating voltage that optimizes reliability of said specific portion of said integrated circuit chips, said group-specific operating voltage being within a group-specific operating voltage range previously assigned to said group.

9. The method of claim 8, said group-specific operating voltage ranges comprising group-specific minimum and maximum voltages within a minimum voltage and a maximum voltage associated with said process distribution.

10. The method of claim 8, said determining said group-specific operating voltage ranges to be assigned to said groups further comprising, for each group:

determining a group fail rate as a function of a selected voltage range; and

iteratively repeating said determining of said group fail rate using different selected voltage ranges.

11. The method of claim 10,

said group fail rate being determined as a sum of chip fail rates of integrated circuit chips within said group divided by a number of said integrated circuit chips in said group, and

each chip fail rate being determined based on multiple failure mechanism fail rates.

12. The method of claim 8, said group-specific operating voltage ranges varying between said groups.

13. The method of claim 8, further comprising:

programming each integrated circuit chip in said group with an identifier associated with said group; and

,

creating a look-up table that associates said identifier with said group-specific operating voltage.

14. The method of claim 8, further comprising programming each integrated circuit chip in said group with said group-specific operating voltage range.

15. A method comprising:

sorting integrated circuit chips manufactured according to a design into groups, said groups being associated with process windows of a process distribution for said design;

determining group-specific operating voltages to be assigned to said groups, said determining comprising, for each group;

identifying a specific selected voltage that achieves a lowest group fail rate; and

using said specific selected voltage as a group-specific operating voltage for said group; and

assigning said group-specific operating voltages to said groups and adjusting sizes of said groups so as to optimize overall reliability of said integrated circuit chips across said process distribution,

said reliability being based on said group fail rate, and

each group being associated with one of said process windows, comprising a specific portion of said integrated circuit chips and being assigned a group-specific operating voltage that optimizes reliability of said specific portion of said integrated circuit chips.

16. The method of claim 15, said group-specific operating voltages being within a minimum voltage and a maximum voltage associated with said process distribution.

17. The method of claim 15, said determining said group-specific operating voltages to be assigned to said groups further comprising, for each group:

determining a group fail rate as a function of a selected voltage; and

iteratively repeating said determining of said group fail rate using different selected voltages.

18. The method of claim 17, said group fail rate being determined as a sum of chip fail rates of integrated circuit chips within said group divided by a number of said integrated circuit chips in said group, and

each chip fail rate being determined based on multiple failure mechanism fail rates.

19. The method of claim 15, further comprising:

programming each integrated circuit chip in said group with an identifier associated with said group; and

,

creating and storing in memory a look-up table that associates said identifier with said group-specific operating voltage.

20. The method of claim 15, further comprising programming each integrated circuit chip in said group with said group-specific operating voltage.