Memory timing circuit

• US 9,489,994 B2
• Filed: 02/02/2016
• Issued: 11/08/2016
• Est. Priority Date: 04/10/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Jefremow, Mihail, Backhausen, Ulrich, Kern, Thomas
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/013,605
• Publication Number:
  US 20160148662A1
• Time in Patent Office: 280 Days
• Field of Search: 365/205
• US Class Current: 1/1
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.

Claims

1. A memory circuit, comprising:

a memory cell configured to provide a charge, voltage, or current to an associated bit-line;

a word-line circuit configured to control a word-line of the memory cell;

a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; and

a sense amplifier comprising a local sense amplifier bias circuit, wherein the sense amplifier is configured to sense the charge, voltage, or current on the bit-line and locally control its local sense amplifier bias circuit by turning the local sense amplifier bias circuit OFF or placing it in low power state, upon determining that the charge, voltage, or current on the bit-line is above a predetermined threshold.