Induced thermal gradients

• US 9,490,003 B2
• Filed: 03/31/2011
• Issued: 11/08/2016
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shoemaker, Kenneth D.
• Primary Examiner(s): Verbitsky, Gail Kaplan
• Application Number:
  US13/077,661
• Publication Number:
  US 20120249218A1
• Time in Patent Office: 2,049 Days
• Field of Search: 374170-172, 374/178, 374/138, 374110-112, 374/29, 374/30, 374/4, 374/1, 374/166, 374/137, 702/130, 702132-136, 702/99, 365/63, 365/211, 365/212, 257/48, 327/512, 327/513, 700/299, 700/300
• US Class Current: 1/1
• CPC Class Codes: G01K 3/08 giving differences of values using thermoelectric elements G01K7/02; giving differentiated values
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

Claims

1. An apparatus comprising:

a first die having a thermal sensor;

a second die stacked with the first die, the second die having a first thermal sensor and a second thermal sensor, the second die in close physical proximity with the first die and the thermal sensor of the first die aligned with the first thermal sensor of the second die, the second thermal sensor of the second die located at a hot spot of the second die, wherein the thermal sensor of the first die does not align with the second thermal sensor of the second die;

a control circuit coupled with the first thermal sensor on the second die and the second thermal sensor on the second die, the control circuit to determine a temperature difference between the first thermal sensor on the second die and the second thermal sensor on the second die;

management logic coupled with the control circuit and the thermal sensor on the first die, the management logic to receive a first value, based on the temperature difference, the first value to indicate a temperature differential range of a plurality of pre-defined temperature differential ranges, and the management logic to further receive a temperature measurement from the thermal sensor on the first die and to determine, based on the first value, an adjustment to the temperature measurement from the thermal sensor on the first die, and to further manage self-refresh parameters of the first die based on the adjustment to the temperature measurement.

2. The apparatus of claim 1 wherein the first die comprises a dynamic random access memory (DRAM) array.

3. The apparatus of claim 2 wherein the management logic modifies refresh rates of the DRAM array based on the temperature gradient on the second die and the temperature measurement from the thermal sensor on the first die.

4. The apparatus of claim 2 wherein the second die comprises a processor core.

5. The apparatus of claim 2 wherein the second die comprises a system on a chip (SoC).

6. A system comprising:

wireless transceiver circuitry coupled with an antenna;

a first die having a thermal sensor;

a second die stacked with the first die, the second die having a first thermal sensor and a second thermal sensor, the second die in close physical proximity with the first die and the thermal sensor of the first die aligned with the first thermal sensor of the second die, the second thermal sensor of the second die located at a hot spot of the second die, wherein the thermal sensor of the first die does not align with the second thermal sensor of the second die;

a control circuit coupled with the first thermal sensor on the second die and the second thermal sensor on the second die, the control circuit to determine a temperature difference between the first thermal sensor on the second die and the second thermal sensor on the second die;

management logic coupled with the control circuit and the thermal sensor on the first die, the management logic to receive a first value, based on the temperature difference, the first value to indicate a temperature differential range of a plurality of pre-defined temperature differential ranges, and the management logic to further receive a temperature measurement from the thermal sensor on the first die and to determine, based on the first value, an adjustment to the temperature measurement from the thermal sensor on the first die, and to further manage self-refresh parameters of the first die based on the adjustment to the temperature measurement.

7. The system of claim 6 wherein the first die comprises a dynamic random access memory (DRAM) array.

8. The system of claim 7 wherein the management logic modifies refresh rates of the DRAM array based on the temperature difference and the temperature measurement from the thermal sensor on the first die.

9. The system of claim 7 wherein the second die comprises a processor core.

10. The system of claim 7 wherein the second die comprises a system on a chip (SoC).

11. A method comprising:

determining a temperature difference between a first thermal sensor and a second thermal sensor on a first die;

transmitting a first value, based on the temperature difference from the first die to a circuit on a second die, the first value indicating a temperature differential range of a plurality of pre-defined temperature differential ranges, the second die stacked with the first die with a thermal sensor of the second die aligned with the first thermal sensor of the first die, the second thermal sensor of the first die located at a hot spot of the first die, wherein the thermal sensor of the second die does not align with the second thermal sensor of the first die;

determining a temperature measurement from a thermal sensor located on the second die;

determining, based on the first value, an adjustment to the temperature measurement from the thermal sensor on the second die; and

based on the adjustment to the temperature measurement, modifying self-refresh parameters of one or more memory circuits on the second die.

12. The method of claim 11 wherein the second die comprises a dynamic random access memory (DRAM) array.

13. The method of claim 12 wherein the circuit modifies refresh rates of the DRAM array based on the temperature measurement from the thermal sensor on the second die.

14. The method of claim 12 wherein the first die comprises a processor core.

15. The method of claim 12 wherein the second die comprises a system on a chip (SoC).