Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
First Claim
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1. A semiconductor memory cell comprising:
- a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
a buried layer terminal electrically connected to said buried layer region.
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
251 Citations
19 Claims
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1. A semiconductor memory cell comprising:
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a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell; a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto; a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and a buried layer terminal electrically connected to said buried layer region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory cell comprising:
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a capacitorless transistor having a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data as charge therein when power is applied to said cell and first and second regions located such that at least a portion of the floating body is located between said first and second regions, said capacitorless transistor configured to function as a bipolar device; a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto; a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and a buried layer terminal electrically connected to said buried layer region. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A semiconductor memory cell comprising:
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a bipolar device configured to store data when power is applied to said cell; and a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto under any one of a plurality of predetermined conditions; wherein one of said predetermined conditions comprises loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said bipolar device is loaded into and stored in said nonvolatile memory; wherein, upon restoration of power to said cell, said data in said nonvolatile is loaded into said bipolar device and stored therein; and wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power. - View Dependent Claims (19)
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Specification