Method and system for accessing a flash memory device

• US 9,490,014 B2
• Filed: 12/10/2015
• Issued: 11/08/2016
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US14/964,958
• Publication Number:
  US 20160196878A1
• Time in Patent Office: 334 Days
• Field of Search: 365/185.11, 365/230.03
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A method comprising:

receiving a chip select signal for activating a plurality of non-volatile memory banks, each non-volatile memory bank being independently operable and comprising control circuitry, row decoding circuitry, column decoding circuitry, and sense amplifier circuitry;

receiving a first data stream at a common interface configured to receive command data, address data and write data, all at different times;

parsing the first data stream to extract a first memory bank identifier of a first of the plurality of non-volatile memory banks;

updating a first memory bank status register corresponding to the first non-volatile memory bank to indicate that the first non-volatile memory bank is busy; and

routing write data of the first data stream between the common interface and a non-volatile memory cell array of the first non-volatile memory bank.

2. The method of claim 1, wherein updating the first memory bank status register comprises setting a bit value in the first memory bank status register.

3. The method of claim 1, further comprising, after routing the write data of the first data stream, updating the first memory bank status register to indicate that the first non-volatile memory bank is ready.

4. The method of claim 1, further comprising:

receiving a second data stream at the common interface;

parsing the second data stream to extract a second memory bank identifier of a second of the plurality of non-volatile memory banks;

updating a second memory bank status register corresponding to the second non-volatile memory bank to indicate that the second non-volatile memory bank is busy; and

during a time period that at least overlaps with a time period for routing the write data of the first data stream, routing write data of the second data stream between the common interface and a non-volatile memory cell array of the second non-volatile memory bank.

5. The method of claim 4, wherein routing write data of the first data stream and routing write data of the second data stream are performed using separate processing threads.

6. The method of claim 4, wherein routing the write data of the second data stream comprises setting a bit value in the second memory bank status register.

7. The method of claim 4, further comprising:

routing the write data, updating the second memory bank status register to indicate that the second non-volatile memory is ready.

8. The method of claim 4, further comprising:

receiving, through the common interface, a read status data stream for status data stored in the second memory bank status register;

parsing the read status data stream to extract the second memory bank identifier of the second non-volatile memory bank; and

(h) routing the status data between the second memory bank status register and the common interface.

9. The method of claim 1, further comprising:

receiving, through the common interface, a read request data stream for read data stored in a second of the plurality of non-volatile memory banks;

parsing the read request data stream to extract a second memory bank identifier of the second non-volatile memory bank;

updating a second memory bank status register corresponding to the second non-volatile memory bank to indicate that the second non-volatile memory bank is busy; and

during a time period that at least overlaps with a time period that routing the write data of the first data stream is performed, routing the read data between a non-volatile memory cell array of the second non-volatile memory bank and the common interface.

10. The method of claim 9, wherein routing the write data of the first data stream and routing the read data are performed using separate processing threads.

11. The method of claim 9, wherein updating the second memory bank status register comprises setting a bit value in the second memory bank status register.

12. The method of claim 9, further comprising:

after routing the read data, updating the second memory bank status register to indicate that the second non-volatile memory bank is ready.

13. The method of claim 1, further comprising:

receiving, through the common interface, a read status data stream for status data stored in the first memory bank status register;

parsing the read status data stream to extract the first memory bank identifier of the first non-volatile memory bank; and

routing the status data between the first memory bank status register and the common interface.

14. A solid state mass storage system comprising:

a controller; and

a plurality of non-volatile memory devices coupled to the controller, each of the plurality of non-volatile memory devices comprising;

a chip select input for receiving a chip select signal from the controller for activating the plurality of non-volatile memory banks, each of the plurality of non-volatile memory banks being independently operable and comprising control circuitry, row decoding circuitry, column decoding circuitry, sense amplifier circuitry, and non-volatile memory cell array;

a common interface for receiving a plurality of data streams, each data stream comprising command data, address data and write data receivable at different times;

a first addressing circuitry for parsing a first data stream to extract a first memory bank identifier of a first of the plurality of non-volatile memory banks;

a first memory bank status register for updating a first memory bank status by setting a bit value in the first memory bank status register to indicate that the first non-volatile memory bank is busy;

a first data register for routing a first write data of the first data stream between the common interface and the non-volatile memory cell array of the first non-volatile memory bank;

a second addressing circuitry for parsing a second data stream to extract a second memory bank identifier of a second of the plurality of non-volatile memory banks, the second data stream being received at the common interface while the first non-volatile memory bank is busy;

a second memory bank status register for updating a second memory bank status by setting a bit value in the second memory bank status register to indicate that the second of the plurality of non-volatile memory banks is busy; and

a second data register for routing a second write data of the second data stream between the common interface and the non-volatile memory cell array of the second non-volatile memory bank while the first non-volatile memory bank is busy.

15. The solid state mass storage system of claim 14, wherein the first memory bank status register further updates the first memory bank status by clearing the bit value in the first memory bank status register to indicate that the first non-volatile memory bank is ready when the routing of the first write data to the non-volatile memory cell array of the first non-volatile memory bank is completed.

16. The solid state mass storage system of claim 14, wherein the second memory bank status register further updates the second memory bank status by clearing the bit value in the second memory bank status register to indicate that the second non-volatile memory bank is ready when the routing of the second write data to the non-volatile memory cell array of the second non-volatile memory bank is completed.

17. The solid state mass storage system of claim 14, wherein the first memory bank status register responds to a read status request from the controller, when the first memory bank identifier is extracted from the read status request, with the status data stored in the first memory bank status register.

18. The solid state mass storage system of claim 14, wherein the second memory bank status register responds to a read status request from the controller, when the second memory bank identifier is extracted from the read status request, with the status data stored in the second memory bank status register.