Wafer-level flipped die stacks with leadframes or metal foil interconnects

• US 9,490,195 B1
• Filed: 10/15/2015
• Issued: 11/08/2016
• Est. Priority Date: 07/17/2015
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Prabhu, Ashok S., Katkar, Rajesh, Moran, Sean
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US14/883,864
• Time in Patent Office: 390 Days
• Field of Search: 257/659
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24175 the item being metallic
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49568 : specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

Claims

1. A stacked microelectronic assembly, comprising:

a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising;

a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;

an encapsulation region having a major surface substantially parallel to the plane of the microelectronic element and a plurality of remote surfaces extending away from the major surface, and the encapsulation region extending from at least one edge surface of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and

a plurality of electrically conductive package contacts at a single one of the remote surfaces spaced apart from the corresponding adjacent edge surface of the microelectronic element of the package, the chip contacts electrically coupled with the package contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic elements are parallel to one another, and the major surfaces of the encapsulation regions of respective microelectronic packages in the stacked assembly are oriented towards one another,

wherein the package contacts are configured for electrically connecting the microelectronic assembly with a corresponding set of substrate contacts at a major surface of a substrate in a state in which the major surface of the substrate is oriented at a substantial angle to the plane of each microelectronic element and is oriented towards each single remote surface of each of the stacked microelectronic packages.

2. The stacked microelectronic assembly as claimed in claim 1, wherein the plurality of package contacts of each package in the stacked assembly are electrically coupled with the corresponding set of substrate contacts at the major surface of the substrate.

3. The stacked microelectronic assembly as claimed in claim 2, wherein a package of the stacked microelectronic packages includes a plurality of the microelectronic elements stacked such that the planes of the stacked microelectronic elements of such package are parallel to one another, wherein the encapsulation region of the package is in contact with the edge surfaces of each of the stacked microelectronic elements of the package, and the chip contacts of each of the stacked microelectronic elements of the package are electrically coupled with the package contacts of the at package.

4. The stacked microelectronic assembly as claimed in claim 1, wherein the encapsulation region of each package contacts at least two of the edge surfaces of the microelectronic element of the package, such that at least two of the remote surfaces of the package are defined by surfaces of the encapsulation region which are spaced apart from the corresponding adjacent edge surfaces.

5. The stacked microelectronic assembly as claimed in claim 1, wherein ends of the package contacts coupled to the microelectronic element of each package extend beyond the remote surface of the encapsulation region of such package.

6. The microelectronic assembly as claimed in claim 1, wherein the package contacts comprise leadframe interconnects, the leadframe interconnects electrically coupled with the chip contacts of the package through leads.

7. The microelectronic assembly as claimed in claim 6, wherein ends of the leadframe interconnects coupled to the microelectronic element in a respective one of the microelectronic packages are flush with or recessed relative to the remote surface of the encapsulation region of such package.

8. A stacked microelectronic assembly, comprising:

a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising;

a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;

an encapsulation region having a major surface substantially parallel to the plane of the microelectronic element and a plurality of remote surfaces extending away from the major surface, the encapsulation region extending from at least one edge surface of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and

a plurality of electrically conductive package contacts at a single one of the remote surfaces spaced apart from the corresponding adjacent edge surface of the microelectronic element of the package, the chip contacts electrically coupled with the package contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic elements are parallel to one another, and the major surfaces of the encapsulation regions of respective microelectronic packages in the stacked assembly are oriented towards one another,

wherein the major surfaces of the encapsulation regions of at least two adjacent microelectronic packages in the stacked assembly are separated from one another by a gap of at least 100 microns, further comprising a heat spreader having at least a portion disposed between the encapsulation regions of the at least two adjacent microelectronic packages in the stacked assembly.

9. The stacked microelectronic assembly as claimed in claim 8, further comprising an adhesive contacting the remote surfaces of each package at which the package contacts are disposed, the major surface of the substrate, and the adhesive surrounding each of the connections between the package contacts and the substrate contacts, wherein features at the major surface of the substrate aligned with the gap define flow paths configured to convey the adhesive across the gap.

10. A microelectronic package, comprising:

a plurality of stacked microelectronic elements each microelectronic element having a front surface defining a plane extending in a first direction and a second direction transverse to the first direction, a plurality of edge surfaces extending away from the plane of the front surface, each microelectronic element having a plurality of chip contacts at the front surface, the microelectronic elements stacked with the planes parallel to one another;

an encapsulation region having a major surface substantially parallel to the plane of each stacked microelectronic element and having a plurality of remote surfaces extending away from the major surface, the encapsulation region extending from at least one edge surface of the microelectronic element to at least one of the remote surfaces which overlies the edge surface; and

a plurality of electrically conductive package contacts disposed at a single one of the remote surfaces, the chip contacts of each of the stacked microelectronic elements electrically coupled with the package contacts,

wherein the package contacts are configured for electrically connecting the microelectronic package with a corresponding set of substrate contacts at a major surface of a substrate in a state in which the major surface of the substrate is oriented at a substantial angle to the plane of the microelectronic element and is oriented towards the single one of the remote surfaces of the microelectronic package.

11. The microelectronic package as claimed in claim 10, wherein the package contacts comprise leadframe interconnects, the leadframe interconnects electrically coupled with the chip contacts through leads coupled to the leadframe interconnects.

12. The microelectronic package as claimed in claim 11, wherein the leads comprise at least one of wire bonds or traces.

13. The microelectronic package as claimed in claim 10, wherein ends of the package contacts coupled to the microelectronic element of each package extend beyond the remote surface of the encapsulation region of such package.

14. The microelectronic package as claimed in claim 10 wherein ends of the leadframe interconnects are flush with or recessed relative to the remote surface of the encapsulation region.

15. The microelectronic package as claimed in claim 10, wherein the edge surfaces of the stacked microelectronic elements are staggered relative to one another.

16. The microelectronic package as claimed in claim 15, wherein at least one of the stacked microelectronic elements is bonded to a die attach pad underlying a surface of the at least one microelectronic element.

17. A microelectronic package, comprising:

a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;

the package having a plurality of remote surfaces, and an encapsulation region contacting at least one edge surface of the microelectronic element and extending away from the at least one edge surface to a corresponding one of the remote surfaces, the encapsulation region having a major surface substantially parallel to the plane of the microelectronic element; and

a plurality of package contacts at a single one of the remote surfaces, the package contacts defined by leadframe interconnects; and

leads electrically coupling the chip contacts of the microelectronic element with the leadframe interconnects, wherein the package contacts are configured for electrically connecting the microelectronic package with a corresponding set of substrate contacts at a major surface of a substrate in a state in which the major surface of the substrate is oriented at a substantial angle to the plane of the microelectronic element and is oriented towards the single remote surface of the microelectronic package.

18. The microelectronic package as claimed in claim 17, wherein the encapsulation region contacts at least two of the edge surfaces of the microelectronic element of the package, such that at least two of the remote surfaces of the package are defined by surfaces of the encapsulation region which are spaced apart from the corresponding adjacent edge surfaces.

19. The microelectronic package as claimed in claim 17, wherein ends of the package contacts extend beyond the remote surface of the encapsulation region.

20. The microelectronic package as claimed in claim 17 wherein ends of the package contacts are flush with or recessed relative to the remote surface of the encapsulation region.

21. The microelectronic package as claimed in claim 17, wherein the leads comprise at least one of wire bonds or traces.

22. The microelectronic package as claimed in claim 17, further comprising a substantially rigid leadframe element adjacent an edge surface of the microelectronic element, the leadframe element having a length dimension parallel to and at least as long as the adjacent edge surface, the leadframe element having substantial cross-sectional area transverse to the length direction such that the leadframe element functions as at least one of a component of a heat spreader thermally coupled to the microelectronic element, or a component of an electromagnetic shield relative to the microelectronic element.

23. The microelectronic package as claimed in claim 22, wherein the leadframe element extends parallel to each of at least three edge surfaces of the microelectronic element.

24. A microelectronic package, comprising:

a microelectronic element having front and rear surfaces each defining a plane, a plurality of edge surfaces between the planes of the front and rear surfaces, the microelectronic element having a plurality of chip contacts at the front surface;

a die attach pad underlying and bonded to one of the front or rear surfaces of the microelectronic element;

the package having a plurality of remote surfaces, and an encapsulation region contacting at least one edge surface of the microelectronic element and extending away from the at least one edge surface to a corresponding one of the remote surfaces, the encapsulation region having a major surface substantially parallel to the plane of the microelectronic element; and

a plurality of package contacts at an interconnect surface being a single one of the remote surfaces, the package contacts electrically coupled with the chip contacts of the microelectronic element, the package contacts defined by leadframe interconnects, wherein a portion of the die attach pad which is not overlain by the microelectronic element bonded thereto is disposed at a second one of the remote surfaces other than the interconnect surface.

25. The microelectronic package as claimed in claim 24, wherein

the portion of the leadframe extends above a height of the die attach pad to at least a height of the package contacts.

26. The microelectronic package as claimed in claim 25, wherein the portion of the leadframe defines a discontinuous metal surface at at least one of the remote surfaces.

27. The microelectronic package as claimed in claim 24, wherein the portion of the leadframe extends above a height of the die attach pad to at least a height of the package contacts, the portion enclosing at least three adjoining edge surfaces of the microelectronic package.

28. The microelectronic package as claimed in claim 24, wherein the package contacts comprise features configured to avoid release of the package contacts at the interconnect surface of the encapsulation region.